CMOS NAND Gate:

Figure (e) represents the CMOS NAND Gate where the T_N1 and T_P1 have the same Input1 and T_N2 and T_P2 has the same Input 2. When Input 1 = Input 2 = 1, T_N1 and T_N2 is on and T_P1 and T_P1 are off. Thus the output is at 0 V. Whereas Input 1 = Input 2 = 0, T_N1 and T_N2 is off and T_P1 and T_P1 are on. Therefore the output is at V_cc. For the case when either one of the inputs is 0, one of the PMOS FET shall be on and therefore the output will be at 1 V. Therefore the CMOS circuit of Figure (e) behaves as a NAND Gate.