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Write Hit Policies:
o Update next level on every write
o Cache is always clean
o A lots of traffic to next level (mostly write)
o Write to cache and mark block dirty
o Update primary memory to eviction
o Less traffic to next ,but more complicated eviction and coherence
o Reads use directly and data array at the same time
o Write use directory first then data array
o How to we pipeline to permit one read or write per cycle?
Ferroelectric RAM is a random-access memory same in construction to DRAM but uses a ferroelectric layer rather of a dielectric layer to achieve non-volatility. FeRAM is one of a gr
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third partial product of 13*11 in binary
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