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Write Hit Policies:
o Update next level on every write
o Cache is always clean
o A lots of traffic to next level (mostly write)
o Write to cache and mark block dirty
o Update primary memory to eviction
o Less traffic to next ,but more complicated eviction and coherence
o Reads use directly and data array at the same time
o Write use directory first then data array
o How to we pipeline to permit one read or write per cycle?
define about data movement
What will occur when contents of register are shifter left, right? This is well known that into left shift all bits will be shifted left and LSB will be appended along with 0 a
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