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Write Hit Policies:
o Update next level on every write
o Cache is always clean
o A lots of traffic to next level (mostly write)
o Write to cache and mark block dirty
o Update primary memory to eviction
o Less traffic to next ,but more complicated eviction and coherence
o Reads use directly and data array at the same time
o Write use directory first then data array
o How to we pipeline to permit one read or write per cycle?
You have two counters counting up to 16, built through negedge DFF, First circuit is synchronous and second is "ripple" as cascading, which circuit has a less propagation delay? Wh
Which of following can not be accessed randomly DRAM, SRAM, ROM or Magnetic tape ? Ans. Magnetic tape cannot be accessed randomly; it can only be accessed sequentially.
Graphs are represented using Adjacency linked list
Instruction Length: Variable-length instructions (Intel 80x86, VAX) need multi-step fetch and decode, but permit for a much more flexible and compressed instruction set.
When calling an external report the parameters or select-options specified in the external report cannot be called.
A two stage non-blocking network requires twice the number of switching elements as the single stage non-blocking network. It is true or false. Ans: It is true that a two st
What is the draw back of assigning one bit position to each control signals? Assigning individual bits to every control signal results in long microinstructions due to the numb
Explain about Bus of register transfer Since a computer has several registers, paths must be provided to transfer information among registors. If separate lines are used amon
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Illustrate about the single inheritance During inheritance, superclass feature may by override by a subclass defining that feature with the same name. The overriding features (
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