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Write Hit Policies:
o Update next level on every write
o Cache is always clean
o A lots of traffic to next level (mostly write)
o Write to cache and mark block dirty
o Update primary memory to eviction
o Less traffic to next ,but more complicated eviction and coherence
o Reads use directly and data array at the same time
o Write use directory first then data array
o How to we pipeline to permit one read or write per cycle?
Accumulator is the register in which Arithmetic and Logic calculations are completed.
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Instruction level This is the initial level and the degree of parallelism is uppermost at this level. The fine grain size is used at statement or instruction level as only few
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Broad Band ISDN handles data rate of about (A) 64 kbps (B) 100 mbps (C) 5.4 mbps (D) 2.048 mbps
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