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Write Hit Policies:
o Update next level on every write
o Cache is always clean
o A lots of traffic to next level (mostly write)
o Write to cache and mark block dirty
o Update primary memory to eviction
o Less traffic to next ,but more complicated eviction and coherence
o Reads use directly and data array at the same time
o Write use directory first then data array
o How to we pipeline to permit one read or write per cycle?
Q. Explain about Dual In line Memory Modules? A DIMM is capable of delivering 64 data bits right away. Usual DIMM capacities are 64MB and up. Every DIMM has 84 gold patted conn
Illustrate what is pascal's principle? Answer:- Pascal's Principle declares that the pressure is transmitted evenly through a liquid. That's why when you pump up a balloon
Visual basic applications have very rich and flexible applications but there is single limitation when using pointer function. Windows API has limited support for function pointers
Q. Insert images in Dreamweaver? You will learn two methods to insert images in Dreamweaver-using Dreamweaver's main menu and using Objects panel. 1. Click anywhere in the l
c-program for the minimum total number of shelves
Action implementing instruction's meaning are a actually carried out by ? Ans. By instruction execution, the meaning of action implementing instruction is actually carried out.
Prove the equations using the Boolean algebraic theorems that is given below A‾BC + AB‾C + ABC‾+ ABC = AB + BC + AC Ans. The equation given is A‾BC + AB‾C + ABC‾+ ABC = AB + BC +
Define parity generator During transmission, at sending end the message is applied to a parity generator, where the needed bit is formed.
Define miss penalty? The extra time required to bring the desired information into the cache is known as miss penalty.
Synchronization Latency Problem: If two simultaneous processes are performing remote loading, then it is not recognized by what time two processes will load, as the issuing proces
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