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Write Hit Policies:
o Update next level on every write
o Cache is always clean
o A lots of traffic to next level (mostly write)
o Write to cache and mark block dirty
o Update primary memory to eviction
o Less traffic to next ,but more complicated eviction and coherence
o Reads use directly and data array at the same time
o Write use directory first then data array
o How to we pipeline to permit one read or write per cycle?
RISC-Means Reduced Instruction Set Computer. A RISC system has decreased number of instructions and more significantly it is load store architecture were pipelining can be executed
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Q. Show the MIPS Addressing Modes? MIPS Addressing Modes MIPS employs various addressing modes: 1. Uses Register as well asimmediate addressing modes for operations.
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