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Write Hit Policies:
o Update next level on every write
o Cache is always clean
o A lots of traffic to next level (mostly write)
o Write to cache and mark block dirty
o Update primary memory to eviction
o Less traffic to next ,but more complicated eviction and coherence
o Reads use directly and data array at the same time
o Write use directory first then data array
o How to we pipeline to permit one read or write per cycle?
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a ship is loaded with a stock of 3 items each unit of item n has a wt wn and vn the max cargo wt the ship can take is the details of 3items are item(n):1 2 3 wt(wn):2 3 1 value(vn)
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Which of following requires refreshing SRAM., DRAM., ROM. or EPROM. ? Ans. DRAM. requires refreshing.
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