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Write Hit Policies:
o Update next level on every write
o Cache is always clean
o A lots of traffic to next level (mostly write)
o Write to cache and mark block dirty
o Update primary memory to eviction
o Less traffic to next ,but more complicated eviction and coherence
o Reads use directly and data array at the same time
o Write use directory first then data array
o How to we pipeline to permit one read or write per cycle?
Explain the working of any one of centralized SPC? Standby mode of operation is the easiest of dual processor configuration operations. Usually, one processor is active and
Case Study - A taxi company has 200 taxies. The company provides its services to all the nine districts in Mauritius, about 20 taxies per district. A taxi is normally attached to
Q. Explain Segment Registers in bus interface unit? These are very significant registers of CPU. Why? We will answer this later. In 8086 microprocessor memory is a byte organiz
What is the working set of a process? The set of pages that are referred by the method in the last "n", references, where "n" is called the window of the working set of the pro
train reservation algorithm
In 1960: The purpose of e-commerce was to exchange the electronic data. In 1970s: Electronic Fund Transfers or EFT was developed which considered as huge impact in the emerging
S tends to aAS/a and A tends to SbA/SS/ba
Q. Explain Passing Parameters Using Pointers ? This method overcomes the drawback of using variable names directly in procedure. It uses registers to pass procedure pointers to
Contact-based keyboards employ switches directly. Though they have a comparatively shorter life they are the most preferred type these days because of their lower cost. Three such
Define Process Control Block (PCB). Process Control Block (PCB): Information related with each process is stored into Process control Block. a) Process state b)
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