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Write Hit Policies:
o Update next level on every write
o Cache is always clean
o A lots of traffic to next level (mostly write)
o Write to cache and mark block dirty
o Update primary memory to eviction
o Less traffic to next ,but more complicated eviction and coherence
o Reads use directly and data array at the same time
o Write use directory first then data array
o How to we pipeline to permit one read or write per cycle?
Which of the memories stores the most number of bits ? Ans. most number of bits stores in 32M x 8 As 2 5 x 2 20 = 2 25 Therefore 1M = 2 20 = 1K x 1K = 2 10 x 2 10
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The micro-instruction cycle can comprises two basic cycles: the fetch and execute. Here in the fetch cycle address of micro-instruction is produced and this micro-instruction is pu
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Using D-Flip flops and waveforms explain the working of a 4-bit SISO shift register. Ans. Serial In-Serail Out Shift Register: Fig.(a) demonstrates a 4 bit serial in-serial out
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