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Q. Why FET is a voltage sensitive device explain from the drain characteristics?
The JFET consists of a thin layer of n-type material with two ohmic contacts,the source S and the drain D ,along with two rectifying contacts ,called the gates G .If a positive voltage is placed between drain and source,electrons will flow from source to drain .This conducting path between the source and the drain is called a channel.
Consider holding the drain source voltage fixed and varying the gate-source voltage .As the gate-source voltage is made negative ,the gate channel pn junction is reverse biased ,increasing the depletion red\gion between the gate and source .This decreases the channel width ,increasing the channel resistance.if the drain-source voltage VDS is kept constant ,the current IDS decreases .when the gate-source voltage is made positive,the depletion region decreases until,for large positive gate-source voltages ,the channel opens .then the pn- junction between gate and channel becomes forward biased and current flows from the gate to the source current Summarizing we find that varying the gate voltage varies the channel width ,and hence the channel resistance .This inturn varies the current from drain to source,IDS .We see that it is the gate-source voltage variation which varies IDS ; thus the FET is a voltage sensitive device ,compared with the junction transistor , which is a current sensitive device.
region of convergence of (Z+2)*(12z-1)/((3z-1)*(4z+1 ))
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