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Why does DMA have priority over the CPU when both request a memory transfer?
The data transfer monitored by DMA controller which is called as DMA channel. The CPU is included only at the starting and end of the transfer, when the CPU wishes to read or write a block of data, it issues a command to DMA Channel by sending read/write operation, address of I/O, number of words to be read or written, as DMA have priority over the CPU when both request a memory transfer.
Explain software process model in brief.
To avoid race condition, the maximum number of processes that may be simultaneously inside the critical section is The maximum number of processes is one to ignore race conditi
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Which of the following is the fastest logic ECL, TTL, CMOS or LSI ? Ans. The fastest logic is ECL.
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