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Why does DMA have priority over the CPU when both request a memory transfer?
The data transfer monitored by DMA controller which is called as DMA channel. The CPU is included only at the starting and end of the transfer, when the CPU wishes to read or write a block of data, it issues a command to DMA Channel by sending read/write operation, address of I/O, number of words to be read or written, as DMA have priority over the CPU when both request a memory transfer.
Why the temporary registers W and Z are named so I mean we start from A,B,C,D,E then H and L coz H stands for higher bit nd L for lower bit of the address pointed by memory pointer
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