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Why a function should have at least one input?
There is no strong reason for this in verilog. I think this restriction isn't removed fin SystemVerilog. Some requirements where inputs are taken from global signal,those functions Don't need any input. A work around is to use a dummy input.
Common Tasks to Accomplish: Once you've worried about what and why you're doing "AI", what has inspired you and how you're going to approach the job, then you just start to th
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Subtraction 11001-10110 using 1's complement Ans. 11001 - 10110 01001 is 1' s Compliment of 10110, so 1 1 0 0 1 + 0 1 0 0 1 ------------------ 1 0 0 0 1 0 Add 1
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