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Why a function should have at least one input?
There is no strong reason for this in verilog. I think this restriction isn't removed fin SystemVerilog. Some requirements where inputs are taken from global signal,those functions Don't need any input. A work around is to use a dummy input.
Normal 0 false false false EN-IN X-NONE X-NONE MicrosoftInternetExplorer4 A loop invariant is
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