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Divide overflow is generated when
(A) Sign of the dividend is dissimilar from that of divisor.
(B) Sign of the dividend is same as that of divisor.
(C) The first part of the dividend is smaller than the divisor.
(D) The first part of the dividend is greater than the divisor.
If the first part of the dividend is greater than the deviser, then the answer should be of greater length, then that can be hold in a register of the system. The registers are of fixed length in any processor.
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If the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops in cascade is ? Ans. The final output of the three T-flip-flops in cascade is 12
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different types of buses with diagram
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