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Question:
a) Write the detailed operation/description of the following mnemonics:
(i) MOVX @DPTR, A (ii) MOVC A, @A + PC (iii) PUSH add
b) What is a subroutine and why a subroutine can be written into the body of a main program.
c) Give one advantage and one disadvantage of using Memory Mapped I/O
d) Describe the two conditions needed in Mode 2 and Mode 3 in Serial Data Communication in order to receive a character properly.
e) Processors running control software in a car or a train will always run that software, and there will be no attempt to run a computer game or spreadsheet program on the same processor. Give two reasons to support this argument.
This test gives a basis for evaluating the load-bearing capability of a sandwich structure when loaded in compression. The specimen should be at least 50 mm wide and the length sho
construction and working of counter flow tray
Exhaust Jet Mixing: Figure shows that the noise from the exhaust jet is the main contributor to the total noise generated by a low by-pass ratio turbo-fan. For a turbo-jet the
what things require for finance project on capital budgeting?
Drop-weight impact towers are frequently used to generate low velocity impact damage. Typically, the falling mass will be instrumented, containing a load-cell for measuring the lo
Q. Explain Rayleigh criterion of resolution. What is meant by resolving power of grating? Ans. Resolving Power (i) Meaning of Resolution : The resolving power of
FUNCTIONAL CHECKS OF CHEMICAL DE-ICING SYSTEMS: Once the correct flow rate of the fluid supply has been established the distribution of the fluid flow over the blades should be
Fire fighting operations - high rise buildings: Inlets that allow the fire service to supplement to water to the sprinklers and to the fire mains are useful additions to the m
Inhibit Gate Occasionally it is required to 'hold' one input to an AND gate at a particular logic level in order to disable the entire gate. One method of representing this sy
logic gate-OR gate Figure shows the symbol that represents a 2 input OR gate together with its truth table. This gate will adopt a 1 state at its output terminal when either
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