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What happens to logic after synthesis, which is driving an unconnected output port that is left open (, that is, noconnect) during its module instantiation?
An unconnected output port in simulation would drive a value however this value doesn't propagate to any other logic. In synthesis, cone of any combinatorial logic which drives the unconnected output would get optimized away during boundary optimisation, that is, optimization by synthesis tools across hierarchical boundaries.
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