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What are the differences between SIMULATION and SYNTHESIS
Simulation <= verify your design.
synthesis <= Check for your timing
Simulation is used to verify functionality of the circuit.. a) Functional Simulation:study of ckt's operation independent of gate delays and timing parameters. b) Timing Simulation :study including estimated delays, verify setup, hold and other timing requirements of devices such as flip flops are met.
Synthesis: One of the foremost in back end steps where by synthesizing is nothing however converting VHDL or VERILOG description to a set of primitives(equations as in CPLD) or components(as in FPGA'S)to fit into target technology.Essentially the synthesis tools convert design description into components or equations.
Q. Describe Miscellaneous and Privileged Instructions? These instructions don't fit in any of above categories. I/O instructions: start I/O, stop I/O, and test I/O. Characteris
#questionabut diffraction ..
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Q. Speed Up - metrics for performance evaluation? Speed up is ratio of time needed to execute a given program employing a specific algorithm on a machine with single processor
Distinguish between uniform scaling differential scaling
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