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What are program-invisible registers?
Ans: the local and global descriptor tables are found in the memory system. To access and specify the address of these tables, program invisible registers used. Program invisible registers aren't directly addressed by software so they are given a name. GDTR (global descriptor table register) and IDTR (interrupt descriptor table register) comprises the base addresses of descriptor table and its limit. Limit of each descriptor table is 16 bits as maximum table length is 64 Kbytes. When protected mode operation is desired, address of the global descriptor table and its limit are loaded into GDTR.
Cache coherence refers to the integrity of data stored in local caches of a shared resource. Cache coherence is a special case of memory coherence. When clients in a system, mainly
Write the truth table of NOR gate. Ans. The truth table for NOR gtae is shown below:
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