What are the different ways synchronize between two clock domains?

The following section describes clock domain interfacing one of the biggest challenges of system-on-chip (SOC) designs is which different blocks operate onto independent clocks.

Integrating these blocks through the processor bus, peripheral busses, memory ports and other interfaces can be troublesome since unpredictable behavior can result while the asynchronous interfaces are not appropriately synchronized. A very general and robust method for synchronizing multiple data signals is a handshake technique as demonstrated in diagram below. It is popular since the handshake technique can easily manage changes in clock frequencies, whereas minimizing latency at the crossing. Nonetheless, handshake logic is considerably more complex than standard synchronization structures.

FSM1 (Transmitter) asserts the req (request) signal, asking the receiver to accept the data onto the data bus. FSM2 (Receiver) usually a slow module asserts the ack (acknowledge) signal, signifying which this has accepted the data. This has loop holes: while system Receiver samples the systems Transmitter req line and Transmitter samples system Receiver ack line, they have completed this regarding their internal clock, therefore there will be setup and hold time violation. To ignore this we go for double or triple stage synchronizers that increase the MTBF and therefore are immune to metastability to a fine extent. The figure below demonstrates how this is done.

Multi- Bulit Sync

Single Bit Metastability Sync