User Account

All Pages

Vhdl, Electrical Engineering

Assignment Help:
Im doing my final year project and Im stuck in vhdl coding. The main mission of this project is to design and build a tap changer which is going to be fitted to power transformers for regulation of the output voltage to required levels for the Micro Grid.
The tap changer system will consist of 9 changers with a 4v step having 9 switches/ Relays. 5 relays will be in the first stage, second stage consist of 3 relays, third stage has got 2 relays and the final stage has 1 relay. The voltage range of the tap changer 399- 431, Tap changer will perform step-up or step-down duties depending on what is requires. ( Tap1-399volts, Tap2 403volts, Tap3 407volts, Tap4 411volts, Tap5 415volts, Tap6 419volts, Tap7 423volts, Tap8 427volts, Tap9 2311volts. )
Im using vhdl programme to control the switches( switch1 to switch 9) using Spartan 3 board and displaying the selected switch on the board. I have written a bit of the the code which is at the bottom and im completely stuck I just need help in finishing the code and have attached the You are my last hope .

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity UPDOWNCOUNTERHOLD is
Port ( Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- Automatic : in STD_LOGIC;--- AUTOMATIC SELECTION
Tap_set : in STD_LOGIC;--- ACTIVATES THE TAP SELECTED
SW : in STD_LOGIC_VECTOR (8 downto 0);---- switch for Tap 1 up to 9
--SSG_input : in std_logic_vector(3 downto 0); -- input to seven segment display
Tap_Output: out STD_LOGIC_VECTOR (8 downto 0);-- Tap output
SSG_out : out STD_LOGIC_VECTOR (6 downto 0);--- SEVEN SEGMENT OUTPUT DISPLAY
AN0 : out STD_LoGIC);
end UPDOWNCOUNTERHOLD;

architecture Behavioral of UPDOWNCOUNTERHOLD is

Constant Max_tap :integer := 9;-- referance for the switches
signal Max_tap_vector:std_logic_vector(3 downto 0);
Signal Auto :STD_LOGIC;---- signal for Automatic
Signal Tap_select :STD_LOGIC;-----signal for Tap_set
Signal Switch :std_logic_vector(3 downto 0);----- signal for SW
Signal Tap_out :std_logic_vector(3 downto 0);----- signal for Tap_Output
Signal Seven_segment :std_logic_vector(6 downto 0);----- signal for the seven segment display
SIGNAL S_SW :std_logic_vector(3 DOWNTO 0);----- SIGANAL FOR SWITCH IN MAUNAL/TAP SELECT
BEGIN
PROCESS(Clock,Reset,Tap_set)

BEGIN

IF (Reset = ''1'') THEN

Tap_out <= "0001"; -- reset to tap 1
Seven_segment <= "1001111" ;-- reset it to display tap 1

ELSIF (rising_edge(Clock)) THEN

IF (Tap_set = ''1'') THEN

Tap_Out<= Switch; -- running on manual output depends on the tap switch which is on

end if;

IF (Tap_out > Max_tap) THEN ---- If the output is more than 9 reset

Tap_Out<= "0001"; --- reset to tap 1
Seven_segment <= "1001111" ;-- reset it to display tap 1

IF (conv_integer(Max_tap)) = Max_tap_vector then

--IF (conv_integer(Max_tap_vector)) = Max_tap then------converting interger
--OTHER_VECTOR<=(others =>''0'');
END IF;
END IF;
End if;
END PROCESS;
PROCESS(SW,Clock)
Begin
--S_SW <= SW(3 DOWNTO 0) ;
case SW is
when "0001"=>SSG_out<= "1001111";
when "0010"=>SSG_out<= "0010010";
when "0011"=>SSG_out<= "0000110";
when "0100"=>SSG_out<= "1001100";
when "0101"=>SSG_out<= "0100100";
when "0110"=>SSG_out<= "0100000";
when "0111"=>SSG_out<= "0001111";
when "1000"=>SSG_out<= "0000000";
when "1001"=>SSG_out<= "0000100";
--nothing is displayed when a number more than 9 is given as input.
when others =>SSG_out<="1111111" ;
end case ;
END PROCESS;
end Behavioral;
?

Related Discussions:- Vhdl

Transformer question, When I read the details of how a transformer works an...

When I read the details of how a transformer works and apply those rules to a transformer where the primary core cross-sectional area is twice that of the secondary, I come up with

Calculate the power dissipated in the amplifier, For the amplifier circuit ...

For the amplifier circuit shown in Figure with R i ≅ ∞,R o ≅ 0,A = 10,R L = 100 , and v in = 1 V, calculate the power dissipated in the amplifier if the voltage at the power-s

Forward bias, Forward bias In forward bias, the p-type is linked with...

Forward bias In forward bias, the p-type is linked with the positive terminal and the n-type is linked with the negative terminal.In forward bias mode the PN junction operati

Find the rotor current, A 2200-V, 1000-hp, three-phase, 60-Hz, 16-pole, wye...

A 2200-V, 1000-hp, three-phase, 60-Hz, 16-pole, wye-connected, wound-rotor induction motor is connected to a 2200-V, three-phase, 60-Hz bus that is supplied by synchronous generato

Characteristics of stepper motors - stepper motor , Characteristics of Ste...

Characteristics of Stepper Motors The main  characteristic of stepper  motors is torque  versus stepping or  pulse  rate. It give the  variation  of torque as a function of pu

Find the current through each resistor, For the circuit in figure, find the...

For the circuit in figure, find the current through each resistor.

Electrical/electronic engineering project, i need a project creating in ele...

i need a project creating in electronic/electrical engineering at HNC level, 3000 words Harvard referencing. it can be about anything in this field or i can give a suggestion

Minimum value of rl that can be used, Verify the minimum & maximum load cur...

Verify the minimum & maximum load current for which the zener diode will keep regulation. Find the minimum value of RL that can be used. The zener diode has V Z = 12V, I ZK =

Working of harmonic distortion analyzer, Q. Explain with the help of a bloc...

Q. Explain with the help of a block diagram the working of harmonic distortion analyzer. OR Write short note on Harmonic distortion analyzer. Sol. Several methods h

The filter capacitor , It is needed to use a half-wave rectifier for a dc p...

It is needed to use a half-wave rectifier for a dc power supply that gives an average dc output voltage of 15 V and a maximum ±1V ripple is permitted. The rectifier feeds a load of

Write Your Message!

Captcha
Order Assignment

Featured Services

Order Now

Popular Subjects

Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

Submit Assignment

Academics

Major Subjects

Majors

Get In Touch

whatsapp: +1-415-670-9521

Phone: +1-415-670-9521

Email: [email protected]

TERMS & POLICIES

HELP & SUPPORT

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd