User Account

All Pages

Vhdl, Electrical Engineering

Assignment Help:
Im doing my final year project and Im stuck in vhdl coding. The main mission of this project is to design and build a tap changer which is going to be fitted to power transformers for regulation of the output voltage to required levels for the Micro Grid.
The tap changer system will consist of 9 changers with a 4v step having 9 switches/ Relays. 5 relays will be in the first stage, second stage consist of 3 relays, third stage has got 2 relays and the final stage has 1 relay. The voltage range of the tap changer 399- 431, Tap changer will perform step-up or step-down duties depending on what is requires. ( Tap1-399volts, Tap2 403volts, Tap3 407volts, Tap4 411volts, Tap5 415volts, Tap6 419volts, Tap7 423volts, Tap8 427volts, Tap9 2311volts. )
Im using vhdl programme to control the switches( switch1 to switch 9) using Spartan 3 board and displaying the selected switch on the board. I have written a bit of the the code which is at the bottom and im completely stuck I just need help in finishing the code and have attached the You are my last hope .

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity UPDOWNCOUNTERHOLD is
Port ( Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- Automatic : in STD_LOGIC;--- AUTOMATIC SELECTION
Tap_set : in STD_LOGIC;--- ACTIVATES THE TAP SELECTED
SW : in STD_LOGIC_VECTOR (8 downto 0);---- switch for Tap 1 up to 9
--SSG_input : in std_logic_vector(3 downto 0); -- input to seven segment display
Tap_Output: out STD_LOGIC_VECTOR (8 downto 0);-- Tap output
SSG_out : out STD_LOGIC_VECTOR (6 downto 0);--- SEVEN SEGMENT OUTPUT DISPLAY
AN0 : out STD_LoGIC);
end UPDOWNCOUNTERHOLD;

architecture Behavioral of UPDOWNCOUNTERHOLD is

Constant Max_tap :integer := 9;-- referance for the switches
signal Max_tap_vector:std_logic_vector(3 downto 0);
Signal Auto :STD_LOGIC;---- signal for Automatic
Signal Tap_select :STD_LOGIC;-----signal for Tap_set
Signal Switch :std_logic_vector(3 downto 0);----- signal for SW
Signal Tap_out :std_logic_vector(3 downto 0);----- signal for Tap_Output
Signal Seven_segment :std_logic_vector(6 downto 0);----- signal for the seven segment display
SIGNAL S_SW :std_logic_vector(3 DOWNTO 0);----- SIGANAL FOR SWITCH IN MAUNAL/TAP SELECT
BEGIN
PROCESS(Clock,Reset,Tap_set)

BEGIN

IF (Reset = ''1'') THEN

Tap_out <= "0001"; -- reset to tap 1
Seven_segment <= "1001111" ;-- reset it to display tap 1

ELSIF (rising_edge(Clock)) THEN

IF (Tap_set = ''1'') THEN

Tap_Out<= Switch; -- running on manual output depends on the tap switch which is on

end if;

IF (Tap_out > Max_tap) THEN ---- If the output is more than 9 reset

Tap_Out<= "0001"; --- reset to tap 1
Seven_segment <= "1001111" ;-- reset it to display tap 1

IF (conv_integer(Max_tap)) = Max_tap_vector then

--IF (conv_integer(Max_tap_vector)) = Max_tap then------converting interger
--OTHER_VECTOR<=(others =>''0'');
END IF;
END IF;
End if;
END PROCESS;
PROCESS(SW,Clock)
Begin
--S_SW <= SW(3 DOWNTO 0) ;
case SW is
when "0001"=>SSG_out<= "1001111";
when "0010"=>SSG_out<= "0010010";
when "0011"=>SSG_out<= "0000110";
when "0100"=>SSG_out<= "1001100";
when "0101"=>SSG_out<= "0100100";
when "0110"=>SSG_out<= "0100000";
when "0111"=>SSG_out<= "0001111";
when "1000"=>SSG_out<= "0000000";
when "1001"=>SSG_out<= "0000100";
--nothing is displayed when a number more than 9 is given as input.
when others =>SSG_out<="1111111" ;
end case ;
END PROCESS;
end Behavioral;
?

Related Discussions:- Vhdl

For sign flag - return instructions, For sign flag  RP ( Return on ...

For sign flag  RP ( Return on Plus ) and RM ( Return on no minus ) Instructions RM returns from the subroutine  to the calling program if sign flag is set  (S=1). The in

Transistor, describe the compensation technique for both Vbe and Icbo

describe the compensation technique for both Vbe and Icbo

Explain junction transistors (npn and pnp), Explain junction transistors (n...

Explain junction transistors (npn and pnp). Junction Transistor: This transistor consists of two p-n junctions combined in one crystal as demonstrated in figure below.

Depletion type mosfet, Depletion type MOSFET The channel is of silico...

Depletion type MOSFET The channel is of silicon. It can be two type of channel that is an n-type or p-type channel; it is still mostly silicon. After that, we take note that

Physical operation of the junction of diode, Q. Physical operation of the j...

Q. Physical operation of the junction of diode? The physical operation of the junction can be described in terms of the charge-flow processes. Usually there is a greater concen

Minimized circuit using or and and not gate, Given S(F) = A'B +'C'D + C'D +...

Given S(F) = A'B +'C'D + C'D +'A'B + 'A B + 'A 'C + 'A D + 'A C A. DRAW A MINIMIZED CIRCUIT USING ONLY OR AND NOT GATES (2 input gates) B. WRITE THE WIRE LIST Example of a

What do you mean by sensors or transducers, Q. What do you mean by Sensors ...

Q. What do you mean by Sensors or Transducers? In almost all engineering applications there arises a need tomeasure some physical quantities, such as positions, displacements,

Design a combination circuit, Design a combination circuit to combine two s...

Design a combination circuit to combine two signals as follows: v 0 = -2 v 1 - 8v 2 - v 3 The following specifications are imposed: R in ≥ 20 k? at all inputs All

Find the frequency of oscillation - amplifier gain, Q. Find the frequency o...

Q. Find the frequency of oscillation, amplifier gain ? The transfer function is found to be where the equation is written as a Laplace transform (s=jw). Analysis of thi

Conductometry experiment, why conductance is not zero at end pont? reply as...

why conductance is not zero at end pont? reply as soon as possible.

Write Your Message!

Captcha
Order Assignment

Featured Services

Order Now

Popular Subjects

Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

Submit Assignment

Academics

Major Subjects

Majors

Get In Touch

whatsapp: +91-977-207-8620

Phone: +91-977-207-8620

Email: [email protected]

TERMS & POLICIES

HELP & SUPPORT

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd