Variable or compound expression - unification algorithm, Computer Engineering

Assignment Help:

Variable or compound expression - Unification algorithm:

Here some things to note regarding this method are: 

(i) There if really trying to match a constant to a different constant fails this means that they are not equal, neither is a variable or compound expression or in list also. However if we considered none of the cases in unify_internal is true to must return failure.  

(ii) In case 1 and 2 in  unify_variable(var,x,my)  check and finds neither inputs have already been substituted. However if we considered if  x  already has a substitution value and var, rather than x and var so there it does similarly if var already has a substitution. 

(iii) In case 3 we see that in  unify_variable  is called as the  occurs-check  case or occur-check. However if we considered this is important to visualize we got to the stage when to complete a unification if we required to substitute X into say, f(X,Y). However if we considered we would write  f(X,Y)  instead of X. After than this still has an  X  in it! Thus we would use to substitute  X  by  f(X,Y)  and again giving us as:  f(f(X,Y),Y)  so it  is obvious why we should never have tried this substitution in the first placeis means that this process will never end. However the occurs check makes sure this isn't going to happen before case 4 returns a substitution. But in realty the rule is:; that you cannot substitute a compound  for a variable so such variable appears in the compound already that you will never get rid of the variable. 

(iv) However if we considered unify_internal(op(x),op(y),mu)) a part of case 5 in unify_internal checks whether the operators of the two compound expressions are the same. Just because of it will return false if, considered an example where it tries to unify two predicates into different names or a  with symbol.


Related Discussions:- Variable or compound expression - unification algorithm

What is a parent class of all java classes, Parent class of all Java classe...

Parent class of all Java classes is? All Java class's parent class is java. lang.object.

How client and server use same protocol port at same time, Can both client ...

Can both client and server use the same protocol port on the same computer at the same time? Explain. Client and server can't use similar port number on similar computer at ide

Explain about mainframes computer, Q. Explain about Mainframes computer? ...

Q. Explain about Mainframes computer? Mainframes, capable of executing in excess of 53 MIPS, are high-performance, general- purpose computers supporting very large databases, r

Explain bit-o-ring technique, Explain bit-O-Ring technique. The micro p...

Explain bit-O-Ring technique. The micro program represents that branches are not always made to a one branch address. This is a direct consequence of combining easy micro routi

Self knowledge - characteristics of an experts system, An experts system ...

An experts system has knowledge that lets it reason about its own operations plus a structure that simplifies this reasoning process. For example if an expert system

The color and plot style, Write a script that will make x and y vectors.  T...

Write a script that will make x and y vectors.  Then, it will ask the user for a color ('red', 'blue', or 'green') and for a plot style ('o', '*').  It will then make a string "pst

What do you mean by interrupts, Q. What do you mean by Interrupts? The ...

Q. What do you mean by Interrupts? The term interrupt is an exceptional event which causes CPU to temporarily transfer its control from presently executing program to a separat

General principles of pruning, General principles of pruning: The gene...

General principles of pruning: The general principles are such that: 1. Given a node N that can be chosen by player one, thus if there is another node, X, along any path,

State the structure of verilog code you follow, State the structure of Veri...

State the structure of Verilog code you follow? A good template for your Verilog file is shown below. // timescale directive tells the simulator the base units and precision

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd