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SR Flip Flop The SR flip flop is an arrangement of logic gates that maintain astable output even after the input are turned off. It has two inputs namely SET input (S
Power Supply and Clock Frequency there are following pins for power supply and clock frequency signals. V CC + 5 V power supply. V SS Ground reference X 1
Why maximum power output is given by a machine at an efficiency of 50 percent?
different coupling methods
Figure shows an isolated three-phase load supplied from a 33 kV/11 kV substation via a 30 km long three-phase 11 kV overhead line. The overhead line has the following series parame
Q. A three-phase, 600-kVA, 2300:230-V,Y-Y trans-former bank has an iron loss of 4400Wand a full-load copper loss of 7600 W. Find the efficiency of the transformer for 70%full load
A 440v 4-pole dc generator takes an armature current of 50A when rotating at 626 rpm. the armature circuit resistance is 0.25 ohms. determine the generated emf?
Power Distribution System The Distribution System contains: - Sub-transmission system in voltage ranges from 33 kV to 220 kV. The energy goes from power subs
Output Characteristics The output or drain characteristic of N - Channel power MOSFET. When gate is made positive with respect to the source an N type channel is formed
SHLD Store HL pair Direct Instruction This instruction is used to store the contents of HL register pair to memory address specified in the instruction and the next ad
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