Target - data phase, Computer Engineering

Assignment Help:

Target abort -computer architecture:

Usually, a target holds DEVSEL# asserted through the final data phase. However, if a target desserts DEVSEL# before disconnecting without data (asserting STOP#), it indicates a target abort, which is a fatal error condition. The initiator may not retry, and usually treats it as a bus error. Note that a target may not dessert DEVSEL# as waiting with TRDY# or STOP# low; it have to do this at the starting of a data phase. After observing STOP#, the initiator will terminate the transaction at the next legal chance, but if it has already signaled its wish to continue a burst (by asserting IRDY# without deserting FRAME#), it is not allowed to dessert FRAME# till the following data phase. A target that requests a burst end (asserting STOP#) can have to wait through another data phase (holding STOP# asserted without TRDY#) before the transaction can stop.

60_Target.png

Data transfer signals on the PCI bus.

550_Target1.png

Read operation on the PCI Bus

2425_Target2.png

Read operation showing the role of the TRDY #, IRDY #

 


Related Discussions:- Target - data phase

Why dynamic RAMs require refreshing, Explain briefly, why dynamic RAMs requ...

Explain briefly, why dynamic RAMs require refreshing? Ans: Due to the charge's natural tendency to distribute itself in a lower energy-state configuration that is, the charg

Technology enablers - information system, Technology Enablers - Information...

Technology Enablers - Information System The progression described above has been enabled by five main factors: Increases in processing capability allowing smaller and

Define memory latency, Define Memory Latency? It is used to refer to th...

Define Memory Latency? It is used to refer to the amount of time it takes to transfer a word of data to or from the memory.

Find out the access time of ROM using bipolar transistors, The access time ...

The access time of ROM using bipolar transistors is about ? Ans. About 1 µ sec is the access time of ROM using bipolar transistors.

Contraposition, Contraposition : The contraposition equivalence is as ...

Contraposition : The contraposition equivalence is as follows:  So it may seem a small strange at first, this means that it appears which we have said nothing in the f

Asembly language programming, Ask question #Minimum Write a program to mask...

Ask question #Minimum Write a program to mask bits D3D2D1D0 and to set bits D5D4 and to invert bits D7D6 of the AX register. 100 words accepted#

Displacement addressing mode - computer architecture, Displacement and  Sta...

Displacement and  Stack Addressing  mode - computer architecture: Displacement Addressing: In displacement addressing mode there are three types of addressing mode. They

What is test requirements, Test requirements are definite in the Requiremen...

Test requirements are definite in the Requirement Hierarchy in TestManager. The requirements hierarchy is a graphical outline of requirements and nested child requirements. Req

How to transmits data in the active message buffer, Q. How to Transmits dat...

Q. How to Transmits data in the active message buffer? int pvm_bcast( char *group, int msgtag ) Transmits data in the active message buffer to a group of processes. msgt

What is combinational circuits, Q. What is Combinational circuits? Comb...

Q. What is Combinational circuits? Combinational circuits are interconnected circuits of gates according to definite rules to generate an output relying on its input value. A w

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd