Target - data phase, Computer Engineering

Assignment Help:

Target abort -computer architecture:

Usually, a target holds DEVSEL# asserted through the final data phase. However, if a target desserts DEVSEL# before disconnecting without data (asserting STOP#), it indicates a target abort, which is a fatal error condition. The initiator may not retry, and usually treats it as a bus error. Note that a target may not dessert DEVSEL# as waiting with TRDY# or STOP# low; it have to do this at the starting of a data phase. After observing STOP#, the initiator will terminate the transaction at the next legal chance, but if it has already signaled its wish to continue a burst (by asserting IRDY# without deserting FRAME#), it is not allowed to dessert FRAME# till the following data phase. A target that requests a burst end (asserting STOP#) can have to wait through another data phase (holding STOP# asserted without TRDY#) before the transaction can stop.

60_Target.png

Data transfer signals on the PCI bus.

550_Target1.png

Read operation on the PCI Bus

2425_Target2.png

Read operation showing the role of the TRDY #, IRDY #

 


Related Discussions:- Target - data phase

Explain about micro-instruction formats, Q. Explain about Micro-instruction...

Q. Explain about Micro-instruction Formats? Now let's focus on format of a micro-instruction. The two widely used formats employed for micro-instructions are vertical and horiz

First-order inference rules - artificial intelligence, First-Order Inferenc...

First-Order Inference Rules -artificial intelligence: Now we have a perfect definition of a first-order model is,in the same way, we may define soundness for first-order infere

Lifo under perpetual inventory procedure, Q. LIFO under perpetual inventory...

Q. LIFO under perpetual inventory procedure? LIFO under perpetual inventory procedure observes Exhibit to see the LIFO method using perpetual inventory procedure. In this proce

State the term- combinational circuit, In a pure combinational circuit is ...

In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? if yes, why? Yes in a pure combinational circuit is it essential to mention all

Explain about barrier, Q. Explain about Barrier? Barrier: No actual tra...

Q. Explain about Barrier? Barrier: No actual transfer of data takes place in this mode unless all the processors involved in the communication execute a particular block, calle

Chains of inference, Chains of Inference: Now we have to look at how t...

Chains of Inference: Now we have to look at how to get an agent to prove a given theorem using various search strategies? Thus we have noted in previous lectures that, there i

Interrupt signal interconnection network (isin), Interrupt Signal Interconn...

Interrupt Signal Interconnection Network (ISIN): When a processor wish to transmit an interruption to another processor, then this interrupt initially goes to ISIN, by which it

Instruction length - assembly language, Instruction Length: Variabl...

Instruction Length: Variable-length instructions (Intel 80x86, VAX) need multi-step fetch and decode, but permit for a much more flexible and compressed instruction set.

What is a demultiplexer, What is a Demultiplexer ? Ans. Demultiplex...

What is a Demultiplexer ? Ans. Demultiplexer has similar circuit as decoder but here E is obtained as the particular input line, the output lines are similar as decode

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd