Target - data phase, Computer Engineering

Assignment Help:

Target abort -computer architecture:

Usually, a target holds DEVSEL# asserted through the final data phase. However, if a target desserts DEVSEL# before disconnecting without data (asserting STOP#), it indicates a target abort, which is a fatal error condition. The initiator may not retry, and usually treats it as a bus error. Note that a target may not dessert DEVSEL# as waiting with TRDY# or STOP# low; it have to do this at the starting of a data phase. After observing STOP#, the initiator will terminate the transaction at the next legal chance, but if it has already signaled its wish to continue a burst (by asserting IRDY# without deserting FRAME#), it is not allowed to dessert FRAME# till the following data phase. A target that requests a burst end (asserting STOP#) can have to wait through another data phase (holding STOP# asserted without TRDY#) before the transaction can stop.

60_Target.png

Data transfer signals on the PCI bus.

550_Target1.png

Read operation on the PCI Bus

2425_Target2.png

Read operation showing the role of the TRDY #, IRDY #

 


Related Discussions:- Target - data phase

8085 programs, what is the theory used to check whether a number is negativ...

what is the theory used to check whether a number is negative or positive?

What is programming paradigm, a. Explain the Programming Paradigm? Discuss ...

a. Explain the Programming Paradigm? Discuss four major programming paradigms. b. State the three basic logic operators available in C++? Write a small program in C++ that uses

Buses - computer architecture, Buses: Execution of 1 instruction ne...

Buses: Execution of 1 instruction need the following 3 steps to be performed by the CPU: I.  Fetch the contents of the memory location pointed at by the computer syst

Explain public switched telephone network, Explain Public Switched Telephon...

Explain Public Switched Telephone Network. PSTN (Public Switched Telephone Network): This is Public Switched Telephone Network (PSTN), which accommodates two types of subscri

Bus master - computer architecture, Bus Master: In  computer system,  ...

Bus Master: In  computer system,  bus  mastering  is  a attribute  supported  by  various  bus  architectures  that  enables  a  device linked to the bus to initiate transacti

Prove using boolean algebra, Q. Prove using Boolean Algebra 1. AB + AC ...

Q. Prove using Boolean Algebra 1. AB + AC + BC' = AC + BC' 2. (A+B+C) (A+B'+C') (A+B+C') (A+B'+C)=A 3. (A+B) (A'+B'+C) + AB = A+B 4. A'C + A'B + AB'C + BC = C + A'B

Dfa, design a dfa which accept all the string over a and b ending with ab o...

design a dfa which accept all the string over a and b ending with ab or ba

Problem solving in parallel-, Problem Solving In Parallel Introduction ...

Problem Solving In Parallel Introduction to Parallel Computing This section examines how a particular task can be broken into minor subtasks and how subtasks can be answer i

What do you mean by decoders, Q. What do you mean by Decoders? Decoder ...

Q. What do you mean by Decoders? Decoder transforms one kind of coded information to other form. A decoder has n inputs and one enable line (sort of selection line) and 2 n ou

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd