Target - data phase, Computer Engineering

Assignment Help:

Target abort -computer architecture:

Usually, a target holds DEVSEL# asserted through the final data phase. However, if a target desserts DEVSEL# before disconnecting without data (asserting STOP#), it indicates a target abort, which is a fatal error condition. The initiator may not retry, and usually treats it as a bus error. Note that a target may not dessert DEVSEL# as waiting with TRDY# or STOP# low; it have to do this at the starting of a data phase. After observing STOP#, the initiator will terminate the transaction at the next legal chance, but if it has already signaled its wish to continue a burst (by asserting IRDY# without deserting FRAME#), it is not allowed to dessert FRAME# till the following data phase. A target that requests a burst end (asserting STOP#) can have to wait through another data phase (holding STOP# asserted without TRDY#) before the transaction can stop.

60_Target.png

Data transfer signals on the PCI bus.

550_Target1.png

Read operation on the PCI Bus

2425_Target2.png

Read operation showing the role of the TRDY #, IRDY #

 


Related Discussions:- Target - data phase

Read after write and write after write - data hazards, RAW  and WAW - Data ...

RAW  and WAW - Data hazards: RAW (read after write) - j tries to read a source before i writes it, hence j wrongly gets the old value .This is the most usual type of

What is assembler, What is Assembler An assembler is a program which ta...

What is Assembler An assembler is a program which takes as input a symbolic language program and produces output as its binary machine language equivalent. The input is known a

Explain the paging unit, Explain the Paging Unit Paging mechanism funct...

Explain the Paging Unit Paging mechanism functions with 4K - byte memory pages or with a new extension available to Pentium with 4M byte-memory pages. In Pentium, with new 4M-b

Interrupt handling - computer architecture, Interrupt handling: Handlin...

Interrupt handling: Handling Interrupts  Several  situations where the processor should avoid interrupt requests Interrupt-enable Interrupt-disable  Typical

Explain client server model, Explain Client Server Model. In the client...

Explain Client Server Model. In the client- server model, communication usually takes the form of a request message from the client to the server asking for several works to be

Determine the block diagram of bcd adder, Determine the block diagram of bc...

Determine the block diagram of bcd adder To add 0110 to binary sum, we use a second 4-bit binary adder. The two decimal digits, together with input-carry, are first added in to

What is optical character recognition, What is Optical character recognitio...

What is Optical character recognition (OCR)  Information on paper is automatically read by a scanner and is then processed/analysed by OCR software and stored in an electronic

How do we prevent selected parameters of a module, How  do  I  prevent  sel...

How  do  I  prevent  selected  parameters  of  a  module  from  being  overridden  during instantiation? If a specific parameter within a module must be prevented from being ov

What is a structure, What is a structure? A structure is a collection o...

What is a structure? A structure is a collection of variables under a single name. These variables can be of different types, and each has a name which is used to select it fro

What do you mean by artificial intelligence, Q. What do you mean by artific...

Q. What do you mean by artificial intelligence? Show the artificial intelligence systems used widely in business. ANSWER: Artificial intelligence (AI) is the science of making

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd