Target - data phase, Computer Engineering

Assignment Help:

Target abort -computer architecture:

Usually, a target holds DEVSEL# asserted through the final data phase. However, if a target desserts DEVSEL# before disconnecting without data (asserting STOP#), it indicates a target abort, which is a fatal error condition. The initiator may not retry, and usually treats it as a bus error. Note that a target may not dessert DEVSEL# as waiting with TRDY# or STOP# low; it have to do this at the starting of a data phase. After observing STOP#, the initiator will terminate the transaction at the next legal chance, but if it has already signaled its wish to continue a burst (by asserting IRDY# without deserting FRAME#), it is not allowed to dessert FRAME# till the following data phase. A target that requests a burst end (asserting STOP#) can have to wait through another data phase (holding STOP# asserted without TRDY#) before the transaction can stop.

60_Target.png

Data transfer signals on the PCI bus.

550_Target1.png

Read operation on the PCI Bus

2425_Target2.png

Read operation showing the role of the TRDY #, IRDY #

 


Related Discussions:- Target - data phase

Write a program to find the area and perimeter of a circle, Write a program...

Write a program to find the area and perimeter of a circle of given radius # include void main() { float radius, area, perimeter, pi=3.14; printf("\nEnter the rad

Explain the programmable rom (prom) - computer memory, Explain the Programm...

Explain the Programmable ROM (PROM) - Computer Memory? This is a kind of ROM that can be programmed using special equipment it can be written to, but only once and this is usef

Data type, Define data type and abstract data type comment upon the signifi...

Define data type and abstract data type comment upon the significant of both

Parallelism conditions, Parallelism Conditions As discussed earlier, pa...

Parallelism Conditions As discussed earlier, parallel computing needs that the segments to be implemented in parallel must be free of each other. Thus, before implementing para

Write about TSR, Write about TSR TPA also holds TSR (terminate and stay...

Write about TSR TPA also holds TSR (terminate and stay resident) programs which remain in memory in an active state until activated by a hot-key sequence or another event like

Describe critical directive in fortan, Q. Describe Critical Directive in FO...

Q. Describe Critical Directive in FORTAN? The critical directive permits one thread executes associated structured block. When one or more threads attain critical directive the

With respect to security which is the better .net or j2ee, With respect to...

With respect to security, which one is the better choice?.Net or J2EE? Explain? As per majority programmers .NET is the best one which have one vendor compare to, the ease of

Search mechanisms in prolog, Search mechanisms in Prolog: Here we can ...

Search mechanisms in Prolog: Here we can needs this simple Prolog program to describe how Prolog searches as:president(X) :- first_name(X, georgedubya), second_name(X, bush).

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd