Target - data phase, Computer Engineering

Assignment Help:

Target abort -computer architecture:

Usually, a target holds DEVSEL# asserted through the final data phase. However, if a target desserts DEVSEL# before disconnecting without data (asserting STOP#), it indicates a target abort, which is a fatal error condition. The initiator may not retry, and usually treats it as a bus error. Note that a target may not dessert DEVSEL# as waiting with TRDY# or STOP# low; it have to do this at the starting of a data phase. After observing STOP#, the initiator will terminate the transaction at the next legal chance, but if it has already signaled its wish to continue a burst (by asserting IRDY# without deserting FRAME#), it is not allowed to dessert FRAME# till the following data phase. A target that requests a burst end (asserting STOP#) can have to wait through another data phase (holding STOP# asserted without TRDY#) before the transaction can stop.

60_Target.png

Data transfer signals on the PCI bus.

550_Target1.png

Read operation on the PCI Bus

2425_Target2.png

Read operation showing the role of the TRDY #, IRDY #

 


Related Discussions:- Target - data phase

++ c, how to find the integral of a function represented by collection of e...

how to find the integral of a function represented by collection of experimental data

Data parallel model - parallel programming model, In the data parallel mode...

In the data parallel model, many of the parallel work focus on performing operations on a data set. The data set is usually organized into a common structure, such as an array or a

What is single program multiple data, Q. What is Single Program Multiple Da...

Q. What is Single Program Multiple Data? A general style of writing data parallel programs for MIMD computers is SPMD (single program, multiple data) means all processors execu

Explain about hexadecimal numbers system, Q. Explain about Hexadecimal Numb...

Q. Explain about Hexadecimal Numbers system? Hexadecimal system has 16 digits that are represented as 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F. A number (F2) H is equivalent to

What is branch prediction logic, What is Branch prediction logic Bran...

What is Branch prediction logic Branch prediction logic in Pentium: Pentium microprocessor uses branch prediction logic to decrease the time needed for a branch caused by in

Define various applications of shift register, Lists out some applications ...

Lists out some applications of Shift Register. Ans: Applications of Shift Registers: a. Serial to Parallel Converter b. Parallel to Serial Converter c. Delay li

Why we need number systems, Q. Why we need number systems? Number syste...

Q. Why we need number systems? Number system is used to signify information in quantitative form. Some of the general number systems are octal, decimal, hexadecimal and binary.

Differences between cisc and risc architectures, Question: a) What is ...

Question: a) What is the main difference between the Princeton and Harvard microprocessor architectures? b) State five main differences between CISC and RISC architectures?

A graph ''g'' with ''n'' nodes is bipartite, A graph 'G' with 'n' nodes is ...

A graph 'G' with 'n' nodes is bipartite if it have  no cycle of odd length.

Prove, state and prove distributive law?

state and prove distributive law?

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd