Target - data phase, Computer Engineering

Assignment Help:

Target abort -computer architecture:

Usually, a target holds DEVSEL# asserted through the final data phase. However, if a target desserts DEVSEL# before disconnecting without data (asserting STOP#), it indicates a target abort, which is a fatal error condition. The initiator may not retry, and usually treats it as a bus error. Note that a target may not dessert DEVSEL# as waiting with TRDY# or STOP# low; it have to do this at the starting of a data phase. After observing STOP#, the initiator will terminate the transaction at the next legal chance, but if it has already signaled its wish to continue a burst (by asserting IRDY# without deserting FRAME#), it is not allowed to dessert FRAME# till the following data phase. A target that requests a burst end (asserting STOP#) can have to wait through another data phase (holding STOP# asserted without TRDY#) before the transaction can stop.

60_Target.png

Data transfer signals on the PCI bus.

550_Target1.png

Read operation on the PCI Bus

2425_Target2.png

Read operation showing the role of the TRDY #, IRDY #

 


Related Discussions:- Target - data phase

Subtraction 11011-11001 using 2's complement, Subtraction 11011-11001 using...

Subtraction 11011-11001 using 2's complement. Ans. 11011 - 11001 = A - B 2's complement of B = 00111 1 1 0 1 1 + 0 0 1 1 1 1 0 0 0 1 0 Ignore carry to get answer as 00010 = 2.

Raid and data stripping, Explained RAID? Ans: High performance devices ...

Explained RAID? Ans: High performance devices tend to be costly. So we can gain very high performance at a reasonable cost using a number of low-cost devices operating in paral

Finest way to get a reference to the viewport, What is finest way to get a ...

What is finest way to get a reference to the viewport from anywhere in the code? Ans) You can use refs config to set a reference on the Application/Controllers

Explain instruction cycle and execution cycle, Q Explain Instruction cycle ...

Q Explain Instruction cycle and Execution cycle. and also explain Instruction Counter, Memory Address Register and Memory Buffer Register.

Pre-os and runtime sub-os functionality, In a raw Itanium, a 'Processor Abs...

In a raw Itanium, a 'Processor Abstraction Layer' (PAL) is incorporated in system. When it's booted PAL is loaded in the CPU and provides a low-level interface which abstracts a nu

Define terms setup time and hold time violation, Define setup time and hold...

Define setup time and hold time, what will occur when there is setup time and hold tine violation, how to overcome it? For Synchronous flip-flops, we have particular requiremen

Define wait protocol, Q. Define Wait protocol? The wait protocol is use...

Q. Define Wait protocol? The wait protocol is used for resolving conflicts that arise due to some multiprocessors requiring same resource. There are 2 kinds of wait protocols:

Show matrix multiplication problem, Q. Show Matrix Multiplication Problem? ...

Q. Show Matrix Multiplication Problem? Let there be 2 matrices M1 and M2 of sizes a x b and b x c correspondingly. If we multiply M1 and M2 product matrix O will be of size a x

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd