State the use parameters and parameter definition modules, Computer Engineering

Assignment Help:

State the Use parameters and parameter definition modules.

Parameters aren't preprocessor definitions and they have scope (for example parameters are associated with specific modules). Parameters  are hence more clean, and if you are in the habit of using a lot of defines; consider switching to parameters. As an instance, let's say we have a test (e.g. test12) that needs many parameters to have specific settings. In your code, you might have this sort of stuff:

module testbench_uart1 (....) 

parameter BAUDRATE = 9600;

...

if (BAUDRATE > 9600) begin

... E.g. use parameter in your code like you might any general variable

... BAUDRATE is completely local to this module and this instance. You might

... have the same parameters in 3 other UART instances and they'd all be different

... values...

Now,  your  test12  has  all  sorts of  settings  required  for  it.  Let's  define  a  special  module  known as testparams  that specifies  all  these  settings.  It  would itself  be  a  module  instantiated  under  testbench:

module testparams;

defparam testbench.cpu.uart1.BAUDRATE = 19200;

defparam testbench.cpu.uart2.BAUDRATE = 9600;

defparam testbench.cpu.uart3.BAUDRATE = 9600;

defparam testbench.clockrate CLOCKRATE = 200; // Period in ns.

... etc ...

endmodule

Above  module  always  has  same  module  name  though you  would  have  many  different filenames;  one  for  each  test.  So,  above  would  be  kept  in  test12_params.v.  Your  Makefile includes appropriate  params file given desired make target. (BTW: You may run across this sort of approach by ASIC vendors who might have a module containing parameters for a memory model or you might see this used to collect together a large number of system calls which turn off timing or warnings on particular troublesome nets, etc.)

 


Related Discussions:- State the use parameters and parameter definition modules

Realize the basic gates with any one universal gate, What is a universal ga...

What is a universal gate? Give examples. Realize the basic gates with any one universal gate. Ans: Universal Gates:   NAND and NOR are termed as Universal gates. The OR, AN

What are the ways to truncate guard bits, What are the ways to truncate gua...

What are the ways to truncate guard bits? 1. Chopping 2. Von Neumann rounding 3. Rounding procedure.

Explain the advantages of object oriented analysis design, Advantages of Ob...

Advantages of Object oriented analysis design The OO approach inherently makes every object a standalone component which can be reused within specific stat problem domains we

Building is into our operational processes, Building IS into our operationa...

Building IS into our operational processes - Information System Although information systems are becoming increasingly prevalent they are not always the correct solution to ev

Elevation of the premature ventricular contraction, As spring approaches, y...

As spring approaches, your design firm has been tasked with designing a two-lane highway in rural Wyoming. The highway descends a hill, crosses a river, and must shift to a para

Subsequent step in karnaugh map, The subsequent step in Karnaugh map is to ...

The subsequent step in Karnaugh map is to map truth table in the map. Mapping is done by putting a 1 in respective square belonging to 1 value in truth table. This mapped map is us

What is dynamic modelling, What is Dynamic Modelling  As you know that...

What is Dynamic Modelling  As you know that computer systems are built from the objects which respond to events. External events arrive at boundary of system; you understan

What do you mean by digital computer, COMPUTER ORGANIZATION & ARCHITECTURE ...

COMPUTER ORGANIZATION & ARCHITECTURE 1. What do you mean by digital computer? Explain the block diagram of a digital computer. 2. What do you mean by Difference Engine? Expl

Pros and cons of assembly language, Pros and Cons of Assembly Language ...

Pros and Cons of Assembly Language The following are a number of advantages / disadvantages of employing assembly language: Assembly Language offers more control over ha

Explain the design reusability of verilog, Explain the Design reusability o...

Explain the Design reusability of Verilog There is no concept of packages in Verilog. Functions and procedures used within a model should be  defined  in  the  module.  To  mak

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd