State the term- use a define function, Computer Engineering

Assignment Help:

State the term- Use a define function

This is almost exactly the same approach as #define and -D compiler arg that C programs use. In your  Verilog  code,  use  a  'define  to  define  the  variable  condition  and  then  use  Verilog preprocessor directives such as 'ifdef. Use the '+define+' Verilog command line option. For an illustration:

... to run the simulation ..

verilog testbench.v cpu.v +define+USEWCSDF

... in your code ...

'ifdef USEWCSDF

initial $sdf_annotate (testbench.cpu, "cpuwc.sdf");

'endif

+define+ can also be filled in from your Makefile invocation, which in turn, can be finally filled in your UNIX prompt command line.

Defines are a blunt weapon since they are very global and you can only do so much with them asthey are a pre-processor trick. Consider the subsequent approach before resorting to defines.

 


Related Discussions:- State the term- use a define function

Analysis of sort bitonic, Analysis of Sort_Bitonic(X) The bitonic sorti...

Analysis of Sort_Bitonic(X) The bitonic sorting network needs log n number of phases for performing task of sorting the numbers. The first n-1 phases of circuit can sort two n/

What is xml, XML is the Extensible Markup Language. It betters the function...

XML is the Extensible Markup Language. It betters the functionality of the Web by letting you recognize your information in a more accurate, flexible, and adaptable way. It is e

Artificial intelligence agents, Artificial Intelligence Agents: We int...

Artificial Intelligence Agents: We introduced what we'll be conversation about in Artificial Intelligence and why those things are necessary. This discussion is of course abou

Find minimum sampling rate of analog signal to be sampled, The analog signa...

The analog signal needs to be sampled at a minimum sampling rate of: (A) 2fs                                               (B) 1/(2fs) (C)  fs/2

What is model view controller (mvc), Model-View-Controller (MVC) is a desig...

Model-View-Controller (MVC) is a design pattern in which "the user input, the modelling of the external world and the visual feedback to the user are explicitly splitted and handle

Define the concept of typing of object oriented analysis, Define the concep...

Define the concept of Typing of object oriented analysis Typing enforces object class such that objects of different classes cannot be interchanged.  Or we can say that, class

Advantages and disadvantages of structured analysis, Advantages and Disadva...

Advantages and Disadvantages of Structured Analysis With time, you will find out that most customers understand structured methods better than object oriented (OO) methods. As

Define addressing modes, Define addressing modes. The dissimilar ways i...

Define addressing modes. The dissimilar ways in which the location of an operand is specified in an instruction are referred to as addressing modes.

What is recursing downwards, What is recursing downwards? And its ways. ...

What is recursing downwards? And its ways. The design process generally works top-down; you start with the higher level operations and proceed to describe lower level operation

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd