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State the term- Use a define function
This is almost exactly the same approach as #define and -D compiler arg that C programs use. In your Verilog code, use a 'define to define the variable condition and then use Verilog preprocessor directives such as 'ifdef. Use the '+define+' Verilog command line option. For an illustration:
... to run the simulation ..
verilog testbench.v cpu.v +define+USEWCSDF
... in your code ...
'ifdef USEWCSDF
initial $sdf_annotate (testbench.cpu, "cpuwc.sdf");
'endif
+define+ can also be filled in from your Makefile invocation, which in turn, can be finally filled in your UNIX prompt command line.
Defines are a blunt weapon since they are very global and you can only do so much with them asthey are a pre-processor trick. Consider the subsequent approach before resorting to defines.
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ASSIGNMENTS
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Prove the following identities a. A ‾B ‾C‾ + A ‾BC ‾ + AB ‾C ‾ + ABC ‾ = C ‾ b. AB + ABC + A ‾ B + AB ‾C = B + AC Ans. a. LHS = A'B'C' + A'BC' + AB'C' + ABC' =
external initiated operations
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