State the structure of Verilog code you follow?

A good template for your Verilog file is shown below.

// timescale directive tells the simulator the base units and precision of the simulation

'timescale 1 ns / 10 ps

module name (input and outputs);

// parameter declarations

parameter parameter_name = parameter value;

// Input output declarations

input in1;

input in2; // single bit inputs

output [msb:lsb] out; // a bus output

// internal signal register type declaration  -  register types (only assigned within always statements).

reg register variable 1;

reg [msb:lsb] register variable 2;

// internal signal. net type declaration - (only assigned outside always statements) wire net variable 1;

// hierarchy - instantiating another module

reference name instance name (

.pin1 (net1),

.pin2 (net2),

.

.pinn (netn)

);

// synchronous procedures

always @ (posedge clock)

begin

.

end

// combinatinal procedures

always @ (signal1 or signal2 or signal3)

begin

.

end

assign net variable = combinational logic;

endmodule