Stack operation and interrupts in microprocessor, Computer Engineering

Assignment Help:

Let us review the operation of the stack within the 68HC11, the stack is a defined area of RAM which is last in first out register (LIFO) . Access to the stack is made via a stack pointer (SP). In the 68HC11 there is only one stack pointer and it is initialised by the LDS command. To transfer data onto the stack we can use the command PSHA or PSHB i.e. push register A or B onto the stack. To remove data simply pull it i.e PULA or PULB, likewise the index registers may be stacked  etc.

      PSHA Push A onto Stack
      PSHB  Push B onto Stack
      PSHX  Push X onto Stack
      PSHY  Push Y onto Stack
      PULA Pull A onto Stack
      PULB  Pull B onto Stack
      PULX  Pull X onto Stack
      PULY  Pull Y onto Stack

Every time data is 'Pushed' onto the stack the Stack pointer is decrements accordingly. The stack is used often by the micro controller for temporary holding data, if a subroutine occurs, the processor stacks the return address and upon the receipt of the RTS command, it pulls the return address automatically. During an interrupt the processor stacks the full details of itself i.e.

  SP    Condition code  
  SP-1    Accumulator A
  SP-2    Accumulator B
  SP-3    Index register X high
  SP-4    Index register X low
  SP-5    Index register Y high
  SP-6    Index register Y low
  SP-7    return address High
  SP-8    Return address Low 
  SP-9    Stack pointer after interrupt

Therefore great care should be taken when using the stack as during an interrupt or subroutine if you place data on the stack you must remove the data before you return from it.


Related Discussions:- Stack operation and interrupts in microprocessor

Give some examples of malicious data, Give some examples of malicious data....

Give some examples of malicious data.  In May 2002, the Norton Anti-Virus software for Windows operating systems detects about 61000 malicious programs. Some of them are named

Why gateways are used during mail transfer, Why Gateways are used during ma...

Why Gateways are used during mail transfer? Email using SMTP effort best while both the sender and the receiver are on the internet and can hold TCP connections in between send

Manipulating logical expressions, Digital circuits also manipulate logicale...

Digital circuits also manipulate logicalexpressione.g. IF account is in credit THEN allow phoneto make calls.So a digital circuit must determine if somethingis TRUE or FALSE. Norma

What is synchronous message passing, Q. What is Synchronous message passing...

Q. What is Synchronous message passing? In Synchronous message passing is executed on synchronous communication network.  In that case sender and receiver processes should be

Evaluate personality defines, Evaluate personality defines? 1. System ...

Evaluate personality defines? 1. System calls: Linux use a software interrupts to change into kernel mode whilst other UNIX system use an inter segment jump. 2. Message n

What is boyce codd normal form, A relation schema R is in BCNF with respect...

A relation schema R is in BCNF with respect to a set F of functional dependencies if for all functional dependencies in F+ of the form a->b, where a and b is a subset of R, at leas

Define minterm and the maxterm - canonical form, Define Minterm and the Max...

Define Minterm and the Maxterm - Canonical Form? Any Boolean expression perhaps expressed in terms of either minterms or maxterms. The literal is a single variable within a t

Higher order predicate logic, Higher Order Predicate Logic : In the v...

Higher Order Predicate Logic : In the very first order predicate logic, we are only allowed to quantify over objects. If we are considered to allow ourselves to quantify over

Time Complexity, how to determiner time complexity of any given polynomial ...

how to determiner time complexity of any given polynomial in data structure?

Bootstrap, The device is packaged in a 80 pin PLCC device as shown.The main...

The device is packaged in a 80 pin PLCC device as shown.The main groupings of the pins are as follows Port A PA0 - PA7 Parallel Port or Timer Port B PB0 - PB7 Parallel Port or High

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd