Software architecture of microprocessor, Computer Engineering

Assignment Help:

The 68HC11 series is based on the Motorola 6800/1 programming instruction set and hence is a fairly simple 8 bit microprocessor. The internal structure of the 6800/1 is shown below

The 6800/1 contains two 8 bit accumulators namely A,B which are used to process/hold data for the Arithmetic/Logic calculations . These can be combined to form one single 16 bit accumulator namely D. Also included are two 16 bits index register IX, IY which are mainly used for  pointing too addresses , but can also be used as a 16 bit store or counter. The next two 16 bits registers are the Program counter (PC) used for holding the current address of the program and the stack pointer (SP) used for holding the address of the next available stack (RAM) position .The final register is a 8 bit register called the condition code register (CCR) , this is used to hold the results of the last ALU operation , each bit (flag) is a particular ALU condition  as shown below

2029_Software Architecture of microprocessor.png

C- Carry/Borrow flag if set indicates that an arithmetic carry/borrow has occurred

V overflow if set indicates that the answer was greater that 8 bits  

Z zero flag if set if the ALU answer has produced a zero  

N - Negative if set this indicates that a negative number has been generated i.e. bit 7 = 1  

I - Interrupt mask if set stops further masked interrupts from happening

H Half carry, if set indicates that a half carry has occurred i.e. ALU result has caused a carry to occur between bit 3,4

X - Interrupt mask, if set indicates that a non masked interrupt has occurred i.e. Reset or XIRQ. Cleared by TAP or RTI

S Stop disable if set disables the use of the stop instruction, if cleared enables the stop command

The 68HC11 instruction set consists of three major groups:
 
          Maths Functions 
          Movement functions
          Processor commands
 
Before we tackle each section we shall first discuss the various addressing modes of each instruction


Related Discussions:- Software architecture of microprocessor

Draw a circuit of TTL gates with Wired-AND connection, Draw a circuit of TT...

Draw a circuit of TTL gates with Wired-AND connection and explain its operation. Wired - AND Connection In digital IC's NAND and NOR gates are most frequently used. For th

Enum statement differ from a typedef statement, How does an enumstatement d...

How does an enumstatement differ from a typedef statement? Typedef statement permits user to define an identifier that would show an exiting data type. The user-defined data

Gantt chart and kiviat diagram, Q. What is Gantt chart and Kiviat diagram? ...

Q. What is Gantt chart and Kiviat diagram? Gantt chart: Gantt chart explains numerous activities of every processor with respect to progress in time in busy -overhead - id

How can we use ordered lists, Q. How can we use Ordered Lists? Lists ha...

Q. How can we use Ordered Lists? Lists having numbered items are termed as ordered lists. They are used when items in the list have a natural order. They can also be used when

Application of connect-4 game, The game Connect-4 is played on a board that...

The game Connect-4 is played on a board that has seven columns. There are six spaces on each column. The board is initially empty. Two players take turns dropping one piece (black

Fuzzy logic - artificial intelligence, Fuzzy set theory provides a means fo...

Fuzzy set theory provides a means for modeling the kind of uncertainty associated with vagueness, with imprecision, and/or with a lack of information regarding a particular element

Show sample instruction format of mips instruction, Q. Show Sample Instruct...

Q. Show Sample Instruction Format of MIPS instruction? Early MIPS architectures had 32-bit instructions and later versions have 64-bit implementations. The first commercial

Hazard (computer architecture), Hazard (computer architecture): In the...

Hazard (computer architecture): In the computer architecture, a hazard is a possible problem that can occurs in a pipelined processor. It concern to the possibility of erroneo

Component fulfil this requirement, A component has the time to failure dist...

A component has the time to failure distribution that is modelled as the Weibull distribution with shape parameter 3 and scale parameter of 36 months. This component is planned to

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd