Simulate the circuit using digital simulation techniques, Electrical Engineering

Assignment Help:

You are the new chief PCB designer for a small company who are about to become heavily involved in the design and realisation of digital timing products. Your management wants to prove the path from design entry to final design data production. Consequently, your first task within the company is to take a design from concept through to completion. Given the nature of the company business, it has been decided the test design will be a digital clock, the block diagram of which is illustrated below. An additional requirement is miniaturisation and the board size should be as small as is practically possible.

2307_Simulate the circuit using digital simulation techniques.png

Each of the elements can be realised from 7400-series TTL in SMD packages. The circuit below shows the internal components and connections for the divide-by-60 block above. The counters are 74160 and the 7-segment BCD is a 7447. Any additional information is readily available in data books and the internet.

  1. Package the components in SMD packages where available.
  2. Simulate the circuit using digital simulation techniques to prove the operation.
  3. Layout the components and the route the board
  4. Generate ALL the files necessary to enable production of the board.

 


Related Discussions:- Simulate the circuit using digital simulation techniques

Explain the working of elecro static precipitator, With the help of neat an...

With the help of neat and clean diagram illustrate the working of Elecro Static Precipitator (ESP). Describe the following: (a) Coal Handling Systems (b) Coal Storage

12345, how do you get better at school

how do you get better at school

Compare memory mapped i/o with i/o mapped i/o, Compare memory mapped I/O wi...

Compare memory mapped I/O with I/O mapped I/O. Memory Mapped I/O Scheme: In this type of scheme there is merely one address space. These address space is explained as all p

Block schematic diagram of ss7, Q. Block schematic diagram of SS7? Leve...

Q. Block schematic diagram of SS7? Levels are as below: Level 1: The Physical Layer Level 2: The Data Link Level Level 3: The signaling network level Level 4: The User Pa

Hamming window and zero padding, This question investigates the effect of e...

This question investigates the effect of extending the data set with zero-padding & of the appropriate time in the workflow to apply a window function. To get finer resolution in t

Draw and explain the circuit of wein bridge oscillator, Q. Draw and explain...

Q. Draw and explain the circuit of Wein bridge oscillator. Obtain the expressions for the (i) frequency of oscillation and (ii) condition for oscillation. Will oscillat

Determine voltage on the self-biased n-channel, Measurements made on the se...

Measurements made on the self-biased n-channel JFET shown in Figure are V GS =-1 V, I D = 4 mA; V GS =-0.5V, I D = 6.25 mA; and V DD = 15 V. (a) Determine V P and I DSS .

Methods of material handling, Q. Show the Methods of material handling? ...

Q. Show the Methods of material handling? Methods of material handling during operations and maintenance activities shall be considered for all facilities to ensure that the fi

Calculate the voltage regulation, The per-phase synchronous reactance of a ...

The per-phase synchronous reactance of a three-phase, wye-connected, 2.5-MVA, 6.6-kV, 60-Hz turboalternator is 10. Neglect the armature resistance and saturation. Calculate the vo

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd