Representation in prolog - logic programs, Computer Engineering

Assignment Help:

Representation in Prolog - Logic Programs:

If we justimpose some additional constraints on first-order logic, so than we get to a representation language knowing as logic programs. There is the main restriction we impose is that all the knowledge we want just to encode is represented as Horn clauses. Hence these are implications that comprise a body and a head is where the predicates in the body are conjoined so they imply the single predicate in the head. Still Horn clauses are universally quantified over whole the variables appearing in them. Then ,there an example Horn clause looks such as:

1736_Representation in Prolog.png

If we notice that the body consists of predicates bi and the head is h(x,y). So there we can make this look a lot much more like the Prolog programs you are needed to writing by making syntactic changes: now first, we turn the implication around and write it as :- like:

∀ x, y, z (h(x,y) :- b (x,y)1 b (x)2 ... b (x,y,z))n

Now finally, we remove the universal quantification it is assumed in Prolog that make the variables capital letters in Prolog requires this to put a full stop at the end:

∀ x, y, z (h(x,y) :- b (x,y), b (x), ..., b (x,y,z))1

Just simplified that we use the notation h/2 to indicate that predicate h has arity 2. In addition we need to call a set of Horn clauses like these a logic program. So for representing knowledge with logic programs is, less expressive than full first order logic,so it can still express lot more of types of information. Obviously in particular, disjunction can be achieved by having alternate or different Horn clauses with the same like head. then, this sentence in first-order logic:

∀x (a(x) b(x) ∨ c(x) d(x))


Related Discussions:- Representation in prolog - logic programs

Minimize the logic function using NAND gate, Minimize the logic function F(...

Minimize the logic function F(A, B, C, D) = ∑ m(1,3,5,8,9,11,15) + d(2,13) using NAND gate with help of K-map. Ans. Realization of given expression by using NAND gates:  In

How free-space is managed using bit vector implementation, How free-space i...

How free-space is managed using bit vector implementation? The free-space list is executed as a bit map or bit vector. Each block is shown by 1 bit. If the block is free, the b

Select statements linked to a logical database, One cannot use SELECT state...

One cannot use SELECT statements in a report program linked to a Logical Database   False. You can use th SELECT statements.

Address phase - computer architecture, Address phase: A PCI bus transa...

Address phase: A PCI bus transaction starts having an address phase. The initiator,  after seeing that it has GNT# and the bus is inactive, drives the target address onto the

What is interaction design process, You are being employed as a novice inte...

You are being employed as a novice interaction designer on a project to develop a public kiosk providing information about the exhibits available in a science museum. Consider how

What methods can be overridden in java, In C++ terminology, all public meth...

In C++ terminology, all public methods in Java are virtual. Thus, all Java methods can be overwritten in subclasses except those that are declared final, private and static.

What is flag, Flag is a flip-flop used to kept the information about the st...

Flag is a flip-flop used to kept the information about the status of a processor and the status of the instruction implemented most recently A software or hardware mark that si

How is EISA bus different from ISA bus, How is EISA bus different from ISA ...

How is EISA bus different from ISA bus? Extended Industry Standard Architecture (EISA) is a 32 bit modification to ISA bus. As computers became larger and had wider data buses,

Carry look-ahead adder and booth''s algorithm, Describe carry look-ahead ad...

Describe carry look-ahead adder? Ans: The input carry required by a stage is directly computed from carry signals obtained from all of the preceding stages i-1,i-2,.....0, rat

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd