Reduced instruction set computer - risc, Computer Engineering

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Reduced Instruction Set Computer (RISC):

As we discussed before most of the modern CPUs are of the GPR (General Purpose Register) type. A few instances of such type of CPUs are the, IBM 360, Intel 80x86 ,Motorola 68xxx and DEC VAX But as these CPUS were obviously better than previous accumulator and stack based CPUs they were yet lacking in various areas:

1. The instructions were of varying length from 1 byte to 6-8 bytes. It is reason of problems with the pre- fetching and pipelining of instructions.

2. ALU (Arithmetic Logical Unit) instructions could have operands that were memory locations. Since the number of cycles it takes to access memory varies so does the all instruction. It isn't good for pipelining, compiler writers and several multiple issues.

3. Most of the ALU instruction had only 2 operands where 1 of the operands is also the destination. It means this operand is cracked in the time operation or it ought to be saved before somewhere.

Therefore in the early 80's the idea of RISC was come. The SPARC project was begun at Berkeley and the MIPS project at Stanford. RISC means Reduced Instruction Set Computer. The ISA is composed of instructions that all have accurately the similar size, typically 32 bits. so they can be pipelined and pre-fetched and successfully. All of the ALU instructions have 3 operands which are just registers. Only memory access is throughout explicit LOAD/STORE instructions. Therefore A = B + C can be assembled as:

LOAD R1, A

LOAD R2, B

ADD R3, R1, R2

STORE C, R3

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