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Examining the write/cycles as shown below
We can see that the bus is designed for asynchronous read/write cycles. The operation of the write cycle is simple in that the address appears on the address bus (*1) and is validated when the address strobe, /AS, goes low (*2). The read/write line is high (*3) and after a predetermined time the upper/lower data lines falls (*4) and data should be input from the data bus (*5) else it is lost. The write cycle is similar to the read cycle, except that read=low and the p outputs the data.
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how does DMA increase system concurrency
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problems of procedure
what is data-processing cycle?
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