Processes vs threads, Computer Engineering

Assignment Help:

One might argue that in general processes are more ?exible than threads. For one thing, they can live in two different machines, and communicate via sockets; they are easy to spawn remotely (e.g. ssh foo.cs.umass.edu "ls -l"); etc. However, using processes requires explicit com- munication and risks hackery. Threads also have their own problems: because they communicate through shared memory, they must run on the same machine and they require thread-safe code.

So even though threads are faster, they are much harder to program. In a sense, we can say that processes are far more robust than threads, since they are completely isolated from other another. Threads, on the other hand, are not that safe, since whenever one thread crashes the whole process terminates.

When comparing processes and threads, we can also analyze the cost of context switches. When- ever we need to switch between two processes, we must invalidate the TLB cache (the so-called TLB shootdown; see Section 6.2.3). Because warming up the TLB takes time, context switches for processes are slower.

On the other hand, when we switch between two threads, it is not necessary to invalidate the TLB, because all threads share the same address space, and thus have the same contents in the cache. In other words, on many operating systems, the cost of switching between threads is much smaller than the cost of switching between processes. Most large-scale systems use a mixture of processes and threads:

threads within a process on one server, communicating via a network socket to similar processes on other servers.


Related Discussions:- Processes vs threads

Full resolution rule - artificial intelligence, Full Resolution Rule - Arti...

Full Resolution Rule - Artificial intelligence: Now that we know about unification, we can correctly describe the complete edition of resolution: p1  ∨ ...  ∨ pj  ∨ ...  ∨ p

Show two way pipelined timing, Q. Show Two Way Pipelined Timing? Figure...

Q. Show Two Way Pipelined Timing? Figure below demonstrates a simple pipelining scheme in which F and E stages of two different instructions are performed concurrently. This sc

menu-driven program, Write a menu-driven program to change a time in secon...

Write a menu-driven program to change a time in seconds to other units (minutes, hours, etc.).  The main script will loop to continue until the user chooses to exit.  Every time in

Design a 32:1 multiplexer, Design a 32:1 multiplexer using two 16:1 multipl...

Design a 32:1 multiplexer using two 16:1 multiplexers and a 2:1 multiplexer Ans. Design a 32 X 1 MUX by using two 16 X 1 MUX and one 2 X 1. Now here total 32 input lines

Instruction-execution cycle, Problem (a) Using a labelled diagram of ...

Problem (a) Using a labelled diagram of an Instruction-Execution cycle, describe how a CPU executes single machine instructions by referring to the five main operations.

Explain the term confidentiality - firewall design policy, Explain the term...

Explain the term Confidentiality - Firewall Design Policy Whilst some corporate data is for public consumption, the vast majority of it should remain private.

Data rate limitations in PSTN's by using nyquist theorem, Explain with the ...

Explain with the help of Nyquist theorem, the data rate limitations in PSTN's. Data rates in PSTNs : A voice channel in a public switched telephone network is band restricted

Execution of micro-program, The micro-instruction cycle can comprises two b...

The micro-instruction cycle can comprises two basic cycles: the fetch and execute. Here in the fetch cycle address of micro-instruction is produced and this micro-instruction is pu

State the selective clear - logic micro operations, State the SELECTIVE CLE...

State the SELECTIVE CLEAR - logic micro operations The selective-clear operation clears to 0 bits in register A only  where there are corresponding 1's in the register B. For

Explain about indexed addressing scheme, In this technique, operand field o...

In this technique, operand field of instruction includes an address and an index register thatcomprises an offset. This addressing scheme is normally used to address the consecutiv

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd