Problem occurs during pipelining , Basic Computer Science

Assignment Help:
While pipelining can cruelly cut the time taken to execute a program, there are troubles that cause it to not work as well as it possibly shall. The three stages of the instruction execution process do not essentially take an equal amount of time, with the time taken for ''execute'' being usually longer than ''fetch''. This makes it much harder to synchronize a variety of stages of the different instructions. Also, some instructions may be dependent on the results of other previous instructions. This can arise when data produced previous needs to be used, or when a conditional branch based on a previous result is used.
One of the easiest ways in which the effects of these troubles can be reduced is by breaking the instruction execution cycle into stages that are more possible to be of an equal duration.
Although, while this may resolve some of the troubles outlined above, it is not without creating further tribulations of its own. Initially, it is not always the case than an instruction will use all six of these stages. Easy load instructions, for example, will not require the use of the final ''write operand'' stage, which would perhaps upset the synchronization. There is also the matter of potential variances within the memory system, as three of the above stages (fetch instruction, fetch operands, write operand) need access to the memory. Many memory management systems would not permit three separate instructions to be accessing the memory immediately, and hence the pipelining would not be as useful as it would first seem.
On top of this, the difficulty of conditional branching and consequence dependant instructions also occurs. This means that the processor requires to be designed well so as to cope with these potential interruptions to the flow of data. As you can tell, there are many subjects which need to be taken into consideration involving to the technique of pipelining. While it is a powerful method for the purpose of increasing CPU performance, it does need careful design and consideration so as to achieve the best possible results.

Related Discussions:- Problem occurs during pipelining

Data structures hw help, Create an implementation of the Ordered Associativ...

Create an implementation of the Ordered Associative Array API using left-leaning red-black trees. Illustrate the use of the API by refactoring your WordBench as a client of Ordered

Explain acl with its types, Question 1 Discuss the two basic operational c...

Question 1 Discuss the two basic operational characteristics of RR Only an active route is redistributed Route redistribution does not impact local route selection

What is electrical energy, the chemical reactions in a battery produce ____...

the chemical reactions in a battery produce ____________, each of which carries energy.

cpp programming assignment help, wrap that computes a customer water bill....

wrap that computes a customer water bill. The bill include Rs.100 water demand charge + a consumption charge of Rs.1.5 for every thousand gallons used. Consumption is figured from

Negative Messages and Blog Related Assignment, Writing Assignment 1: You...

Writing Assignment 1: Your boss wants to know about the risks of corporate blogging and recommended policies to prevent companies from liability. Write a properly informal for

Data structuures, write a fuctions for MIDSQUARING hashing technique

write a fuctions for MIDSQUARING hashing technique

Explain FDM : Frequency Division Multiplexing, Frequency Division Multiplex...

Frequency Division Multiplexing : FDM is an analog technique that is applied when he bandwidth of link is greater than the combined bandwidth of the signals to be transmitted. a

Define z-transform of sequence x[n], QUESTION (a) Define z-transform o...

QUESTION (a) Define z-transform of sequence x[n]. (b) A causal LTI system has impulse response h[n], for which the z-transform is                     H(z) = (1+z -1

Dataflow modeling for dsp design, Dataflow Modeling for DSP Design The ...

Dataflow Modeling for DSP Design The necessary components in the research of application-specific computer architectures are: 1) a clearly identified set of problems that can b

Electronic digital, Design a BCD to excess 3 code converter using minimum n...

Design a BCD to excess 3 code converter using minimum number of NAND gates.

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd