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What is a Priority Interrupt?
Ans: A priority interrupt is a type of interrupt that establishes a priority over the many sources to determine which condition is to be serviced first when 2 or more requests arrive simultaneously.
Describe bus.
Ans: When a word of data is transferred among units, all the bits are transferred in parallel over a set of lines which is called bus. In apart to the lines that carry the data, the bus must have lines for control purposes and address.
Explain synchronous bus.
Ans: Synchronous buses are the ones of the bus in which each item is transferred during a time slot (clock cycle) known to the source and destination units both. Synchronization can be gain by connecting both units to a common clock source.
Q. Standards used for development of a system? Documentation standards: It must be an ongoing activity at the time of system development life cycle. Quality Standards:
Discuss the CSMA/CD and CSMA/CA protocols. CSMA/CD: this is an access method used mainly with LANs configured in a bus topology. Along with CSMA/CD, any station (node) can se
Program Level This is normally the liability of OS (operating system) that runs processes simultaneously. Different programs are generally independent of each other. So paralle
Why EPROM chips are mounted in packages that have transparent window? Since the erasure needs dissipating the charges trapped in the transistors of memory cells. This can be co
Discuss about OS as system software? OS is a large program or actually a collection of routines that is used to control the sharing of and interaction between various computer
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How does multiplexer know which line to select? This is managed by select lines. The select lines provide communication among different components of a computer. Now let's see
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What do you mean by underflow and overflow of data? Underflow and overflow of data: When the value of the variable is either too long or too small for the data type to hold,
What is MASK OPERATION The mask operation is similar to selective-clear operation except which the bits of Aare cleared only where there are corresponding 0's in register B. th
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