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In a raw Itanium, a "Processor Abstraction Layer" (PAL) is integrated into the system. When it is booted the PAL is loaded into the CPU and gives a low-level interface that abstracts some instructions and gives a mechanism for processor updates distributed via a BIOS update.
During BIOS initialization an additional layer of code, the "System Abstraction Layer" (SAL) is loaded that gives a uniform API for execution-specific platform functions.
On top of the PAL/SAL interface sits the "Extensible Firmware Interface" (EFI). EFI is not part of the IA-64 architecture but by convention it is needed on all IA-64 systems. It is a easy API for access to logical aspects of the system (display, storage, keyboard, etc) combined with a lightweight runtime environment (same to DOS) that allows basic system administration tasks such as configuring storage adapters, flashing BIOS and running an OS boot-loader.
Once the OS has been booted, some aspects of the PAL/SAL/EFI stack remain resident in memory and can be accessed by the OS to perform low-level tasks that are implementation-dependent on the underlying hardware.
In this segment, we will give very brief details of registers of a RISC system known as MIPS. MIPS is a register-to-register or load/store architecture and employs three address
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