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Power Pc :
A Power PC is a microprocessor designed to meet a standard, which was combining designed by Motorola, Apple and IBM. The PowerPC standard specifies a common instruction set architecture (ISA), allowing anybody to fabricate PowerPC processors and design, which will run the similar code. The PowerPC architecture is based on the IBM POWER architecture used in IBM's RS/6000 workstations. Currently Motorola and IBM are working on PowerPC chips.
The PowerPC architecture specifies 64 bit and32 bit both data paths. Early implementations will be 32 bit; future higher performance implementation will be 64 bit. A PowerPC has 32 general purpose (integer) registers (32- or 64 bit) and 32 floating point (IEEE standard 64 bit) registers.
Assembly Language: Inside the 8085, instructions are really stored like binary numbers, not a very good manner to look at them and very difficult to decipher. An assembler is
Pointer and Index Registers The pointers contain offset within the specific segments. The pointers BP, IP and SP generally containoffsets within thedata, code and stack segment
DEC : A powerful new Alpha 64 bit RISC computer chip was introduced in the year 1977, as new VAX (Virtual Address Extension) Computer. The VAX was 32 bit computer line based on
Zero flag: The next line compares the value in register. A with the value 1. If they are equivalent, the Zero flag is set (to 1). The next line then jumps to start: only if th
CMPS : Compare String Byte or String Word:-The CMPS instruction may be utilized to compare two strings of Words or byte. The length of the string ought to be stored in the CX. If
LODS : Load String Byte or String Word:- The LODS instruction loads AL/AX register by the content of a string pointed to by DS:SI register pair. The SI is automatically modifie
RCR: Rotate Right through Carry:- This instruction rotates the contents bit-wise of the destination operand right by the specified count through carry flag (CF). For each operati
BINARY TO GRAY CONVERSION
DAS: Decimal Adjust after Subtraction:- This instruction converts the result of subtraction operation of 2 packed BCD numbers to a valid BCD number. The subtraction operation has
Format of Control Register The format for the control register is given in Figure. Bit 0 of this register might be one before data may be output and bit two might be one
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