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Power Pc :
A Power PC is a microprocessor designed to meet a standard, which was combining designed by Motorola, Apple and IBM. The PowerPC standard specifies a common instruction set architecture (ISA), allowing anybody to fabricate PowerPC processors and design, which will run the similar code. The PowerPC architecture is based on the IBM POWER architecture used in IBM's RS/6000 workstations. Currently Motorola and IBM are working on PowerPC chips.
The PowerPC architecture specifies 64 bit and32 bit both data paths. Early implementations will be 32 bit; future higher performance implementation will be 64 bit. A PowerPC has 32 general purpose (integer) registers (32- or 64 bit) and 32 floating point (IEEE standard 64 bit) registers.
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The modes are determined by the contents of the control register, whose format is given in Figure These modes are: Mode 0: If a group is in mode 0, it is divided into 2 sets.
AND: Logical AND: This instruction bit by bit ANDs the source operand that might be an immediate, or a memory location or register to the destination operand that might be a memor
AAS: ASCII Adjust AL After Subtraction AAS instruction correct the result in the AL register after subtracting operation of two unpacked ASCII operands. The result is in unpacked
DAS: Decimal Adjust after Subtraction:- This instruction converts the result of subtraction operation of 2 packed BCD numbers to a valid BCD number. The subtraction operation has
Addressing mode of 8086 : Addressing mode specify a way of locating operands or data. Depending on the data types used the memory addressing modes and in the instruction ,
String Manipulation Instruction A series of words or data bytes are available in memory at consecutive locations, to be mention to individually or collectively, are known as by
TEST : Logical Compare Instruction: The TEST instruction performs bit by bit logical AND operation on the 2 operands. Each bit of the result is then set to value I, if the equival
what is double hashing
Intel's 8237 DMA controller : 1) The 8237 contain 4 independent I/O channels 2) It contains 27 registers, 7 of which are system-wide registers and 5 for each channel. 3)
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