PCI bus transactions:

PCI bus traffic is prepared of a series of PCI bus transactions. Each transaction is build up of an address phase that is followed by 1 or more data phases. Direction of the data phases can be from initiator to target (write transaction) or vice-versa (read transaction), but all of the data phases ought to be in the similar direction. Either party can pause or halt the data phases at any specific point. (One common instance is a low-performance PCI device that does not support burst transactions, and always halts a transaction after the first data phase.)Any PCI device can initiate a transaction. Firstly, it might request permission from a PCI bus arbiter on the motherboard. The arbiter gives permission to 1 of the requesting devices. The initiator start the address phase by broadcasting a 32-bit address plus a 4-bit command code, then waits for an objective to respond. All other devices inspect this address and one of them responds a few cycles later.

64-bit addressing is done by using a 2-stage address phase. The initiator broadcasts the low 32 bits address, accompanied by a special "dual address cycle" command code. Components that don't support 64-bit addressing may not respond simply to that command code. In the next cycle, the initiator transmits the high 32 bits address, with adding the real command code. The transaction operates identically from that particular point. To ensure compatibility having 32-bit PCI devices, it is prohibited to use a dual address cycle if it is not necessary, for example if the high-order address bits are all 0.Though the PCI bus transfers 32 bits /data (per data) phase, the initiator transmits a 4-bit byte mask mentioning which 8- bit bytes are to be considered significant. In specific, a masked write necessity affects only on the desired bytes in the target PCI device.