PC Bus and Interrupt System

The PC Bus utilized a bus controller, address latches, and data transceivers (bidirectional data buffers).

1) Bus controller :( Intel 8288 Bus Controller) coordinates activities on bus. It converts clock signal and CPU status into bus control signals. These control signals direct operations  of data transceivers, latches and the I/O bus

2) Address latches:  these are buffers for the address lines. They consider 2 reasons, fill the speed gap between the CPU and other devices; and permit the CPU pins to be utilized for other purposes.

3) Data transceivers:  it is bidirectional data buffers

Interrupt processing: interrupt processing follows the below steps:

• When an external device requests for an interrupt then the CPU initiates a special sequence of bus cycles, that called Interrupt-acknowledge sequence
• The external device known the interrupt-acknowledge sequence by decoding the bus control signals

Once the external device recognizes the acknowledge, then it places the interrupt vector number on the data bus (through interrupt controller, in the case of IBM PC)

After  the  CPU  receives  the  interrupt  vector,  it  start  the  standard  interrupt-initiation   sequence: forming the interrupt vector address; then  it is starting execution of the interrupt handler routine.