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Write a Verilog code for synchronous and asynchronous reset? Synchronous reset, synchronous means clock dependent so reset must not be present in sensitivity disk eg: alway
Define setup time and hold time, what will occur when there is setup time and hold tine violation, how to overcome it? For Synchronous flip-flops, we have particular requiremen
What is parallel adder? Draw and explain block diagram for 4 bit parallel adder. Ans: By using full adder circuit, any two bits can be added along with third input like a ca
In a report with an LDB attribute, you do not have to explain how the information should be retrieved from the database tables, but only how the data should be shown on the screen.
Define memory address map? Addressing of memory can be established by means of a table that specifies the memory address assigned to each chip. The tables, known as memory addr
The decimal equivalent of (1100) 2 is ? Ans. (1100) 2 = (12) 10
Loosely Coupled Systems These systems don't share global memory since shared memory concept increases the problem of memory conflicts, which consecutively slows down the
What are the gates required to build a half adder ? Ans. The gates needed to build a half adder are EX-OR gate and AND gate as shown below the logic diagram of half adder:
An expert system has death that is it operate effectively in a narrow domain containing difficult challenging problems. Thus the rules in an experts systems are necessarily co
Which transmission mode is used for data communication along telephone lines? Serial transmission mode is utilized for data communication along telephone lines.
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