Odd-even merging circuit, Computer Engineering

Assignment Help:

Odd-Even Merging Circuit

Let's firstly understand the idea of merging two sorted sequences using an odd-even merging circuit. The functioning of a merging circuit is as given below:

 1)  Let there be 2 sorted sequences A= (a1, a2, a3, a4......... am) and B= (b1, b2, b3, b4......... bm) that are needed to be merged. 

2)  With help of a merging circuit (m/2, m/2) merge the odd indexed numbers of two sub sequences it implies that (a1, a3, a5......... am-1) and (b1, b3, b5......... bm-1) and so resulting in sorted sequence (c1, c2, c3......... cm).

3) Afterwards, with the help of a merging circuit (m/2, m/2) merge the even indexed numbers of the two sub sequences it implies that (a2, a4, a6......... am) and (b2, b4, b6......... bm) and so resulting in sorted sequence (d1, d2, d3......... dm).

4)  The last output sequence O= (o1, o2, o3......... o2m) is attained in the given below manner: o1 = a1 and o2m = bm .In broad the formula is as following: o2i = min (ai+1, bi) and o2I+1 = max(ai+1,bi ) for i=1,2,3,4..........m-1. 

Now let's take an illustration for merging the 2 sorted sequences of length 4 it implies that A= (a1, a2, a3, a4) and B= (b1, b2, b3, b4). Assume numbers of sequence are A= (4, 6, 9, 10) And B= (2, 7, 8, 12). The circuit of merging the two provided sequences is explained in Figure.

1690_Odd-Even Merging Circuit.png

Figure: Merging Circuit


Related Discussions:- Odd-even merging circuit

What will be the output of JK flipflop for J = 0 and K=1, For JK flipflop J...

For JK flipflop J = 0, K=1, the output after clock pulse will be ? Ans. J=0 and K=1, such inputs will reset the flip-flop, after the clock pulse. Therefore whatever be the earlie

Development tools environment , Main Objectives: • MPLAB In-Circuit Debugg...

Main Objectives: • MPLAB In-Circuit Debugger (ICD 2) functionality • ICD 2 Connection design • MPLAB ICD 2 setup with the PC and Interface board designed • I²C Protocol buses tech

Explain high level data link control, Explain High Level Data Link Control....

Explain High Level Data Link Control. HDLC - it is High Level Data Link Control: Protocol Overall explanation: Layer 2 of the OSI model is the data link layer. One of the

Arbitrary categorisation - learning decision trees, Arbitrary categorisatio...

Arbitrary categorisation - learning decision trees: Through visualising  a set of boxes with some balls in. There if all the balls were in a single box so this would be nicely

Explain about interrupt-processing sequence, Q. Explain about Interrupt-Pro...

Q. Explain about Interrupt-Processing Sequence? The occurrence of an interrupt fires a numbers of events both in processor hardware and software. Figure below displays a sequen

Explain internal organization of bit cells in a memory chip, Explain with n...

Explain with neat diagram the internal organization of bit cells in a memory chip. Memory cells are usually organized in the form of an array, in which every cell is capable of

Define operation code, Define Operation code. The Operation code of an ...

Define Operation code. The Operation code of an instruction is a group of  bits that explain such operations as add, sub, ,shift, mul and complement.

Explain about the acoustic tablet, Explain about the Acoustic tablet Ac...

Explain about the Acoustic tablet Acoustic (or sonic) tablet use sound waves to detect a stylus position. Either strip microphones or point microphones can be used to detect th

What is an "on input filed" statements, What is an "on input filed" stateme...

What is an "on input filed" statements? ON INPUT The ABAP/4 module is known as only if a field having the Value other than the initial Value. This initial Value is explain

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd