New asic design flow, Electrical Engineering

Assignment Help:

There is a requirement to propose a new ASIC design flow within your company, from VHDL design capture through to GDSII tape out.  It is very important that the flow includes all the tools, and you explain all data formats, that will be required.  You should choose an example application design to help with your discussion.

Your report for this assignment should include;

1.    Suggest a design flow (graphically and with an accompanying discussion), to take a design from VHDL to GDSII.

2.    Detail all the tools chosen, together with their suppliers.  Include the features of the tool and the data formats that they will accept, and cost the design flow for implementation.

3.    Explain what an ASIC library comprises, and suggest a suitable technology for your chosen application.  Give recommendations on choosing ASIC libraries for any application.

Provide all references for all relevant material, and be aware that the report will be checked for originality via the TurnItIn software.


Related Discussions:- New asic design flow

What is the load resistance in ohms, Q. A 5-MVA, 66:13.2 kV, three-phase tr...

Q. A 5-MVA, 66:13.2 kV, three-phase transformer supplies a three-phase resistive load of 4500 kW at 13.2 kV. What is the load resistance in ohms as measured fromline to neutral on

Determine the efficiency, Q. (a) Consider a three-phase star or wye half-wa...

Q. (a) Consider a three-phase star or wye half-wave recti?er with a purely resistive load R. Determine: (i) efficiency, (ii) formfactor, (iii) ripple factor, (iv) TUF, and (v) PIV

Illustrates power dissipation management in embedded system, Illustrates ab...

Illustrates about the power dissipation management in embedded system? Power Dissipation Management a. Clever real-time programming through Wait and Stop instructions b.

Projects, I want project ideas.

I want project ideas.

Explain the signals hold and sid, Explain the signals HOLD, READY and SID ...

Explain the signals HOLD, READY and SID HOLD indicates that a peripheral such as DMA controller is requesting the use of address bus, data bus and control bus. READY is used to

Delay line in CRO, why we use delay line in CRO what happens if we not use ...

why we use delay line in CRO what happens if we not use it?

Quantizer, Q. When the quantum step size δv and the step size of f (t) are ...

Q. When the quantum step size δv and the step size of f (t) are the same as in , the quantizer is said to have a gain of unity. If, on the other hand, the quantizer has a gain of K

Dynamics of electrical machines, 1. Modeling of Armature and Field Controll...

1. Modeling of Armature and Field Controlled DC motors: Steady state and dynamic models; development of block diagrams;  assumptions used; complexity involved in realistic models;

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd