Multiple bus architecture - computer architecture, Computer Engineering

Assignment Help:

Multiple bus architecture:

One solution to the bandwidth restriction of a single bus is to simply add extra buses. Consider the architecture indicated in given figure that contains N processors, P1 P2 PN, each containing its own private cache, and all linked to a shared memory by B buses BB, B1, B2. The shared memory consists of M interleaved banks M1 M2,MM to permit simultaneous memory requests concurrent access to the shared memory. It ignores the loss in performance that happen if those accesses have to be serialized, which is the case when there is only 1 memory bank. Each processor is linked to every bus and so is each memory bank. When a processor requires accessing a specific bank, it has B buses from which to select. Therefore each processor- memory pair is linked by various redundant paths, which implies that the failure of 1 or more paths can, principally, be tolerated at the cost of some degradation in system performance.

In a multiple bus system many processors may try to access the shared memory simultaneously. To deal with this problem, a policy might be implemented that allocates the available buses to the processors making requests to memory. In particular case, the policy might deal with the case when the number of processors exceeds from the B. For performance point of view this allocation has to be performed by hardware arbiters which, as we will see, add significantly to the difficulty of the multiple bus interconnection networks.

PCout, R=B, MARin, Read, IncPC

  • WFMC
  • MDRoutB, R=B, IRin
  • R4out, R5outB, SelectA, Add, R6in, End.

389_Multiple bus architecture.png


Related Discussions:- Multiple bus architecture - computer architecture

Java, what is java?

what is java?

Explain about the term e-cash, Explain about the term E-Cash. E-cash is...

Explain about the term E-Cash. E-cash is cash demonstrated by two models. E-cash has one is on-line form of e-cash, that is introduced by DigiCash that permits for the completi

Show programming based on data parallelism, Q. Show Programming Based on Da...

Q. Show Programming Based on Data Parallelism? In data parallel programming model the focal point is on data distribution. Every processor works with a part of data. We will co

Define the refresh rates and frame rate, Q. Define the Refresh Rates and fr...

Q. Define the Refresh Rates and frame rate? A special circuit known as the Video Controller scans video memory one row at a time and reads data value at each address sending th

Provide constructors, For this assignment, fill out the following class:   ...

For this assignment, fill out the following class:   class person { private:   string firstName;   string lastName;   int weight; public:   . . . }; You should provide cons

How to use http and world wide web, Q. How to use Http and World Wide Web? ...

Q. How to use Http and World Wide Web? Http and World Wide Web One of the most frequently used services on the Internet is the World Wide Web (WWW). The application proto

Classes, write a program to copt values of object without using copy constr...

write a program to copt values of object without using copy constructor or = operator

Find out the decimal equivalent of binary number, The decimal equivalent of...

The decimal equivalent of Binary number 10101 is ? Ans. 1x2 4 + 0x2 3 +1x2 2 +0x2 1 + 1x2 0 = 16 + 0 + 4 + 0 + 1 = 21.

Explain the daa instruction, Explain the DAA DAA instruction follows th...

Explain the DAA DAA instruction follows the ADC or ADD instruction to adjust the result into a BCD result. DAA instruction functions only with the AL register, this addition sh

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd