Multiple bus architecture - computer architecture, Computer Engineering

Assignment Help:

Multiple bus architecture:

One solution to the bandwidth restriction of a single bus is to simply add extra buses. Consider the architecture indicated in given figure that contains N processors, P1 P2 PN, each containing its own private cache, and all linked to a shared memory by B buses BB, B1, B2. The shared memory consists of M interleaved banks M1 M2,MM to permit simultaneous memory requests concurrent access to the shared memory. It ignores the loss in performance that happen if those accesses have to be serialized, which is the case when there is only 1 memory bank. Each processor is linked to every bus and so is each memory bank. When a processor requires accessing a specific bank, it has B buses from which to select. Therefore each processor- memory pair is linked by various redundant paths, which implies that the failure of 1 or more paths can, principally, be tolerated at the cost of some degradation in system performance.

In a multiple bus system many processors may try to access the shared memory simultaneously. To deal with this problem, a policy might be implemented that allocates the available buses to the processors making requests to memory. In particular case, the policy might deal with the case when the number of processors exceeds from the B. For performance point of view this allocation has to be performed by hardware arbiters which, as we will see, add significantly to the difficulty of the multiple bus interconnection networks.

PCout, R=B, MARin, Read, IncPC

  • WFMC
  • MDRoutB, R=B, IRin
  • R4out, R5outB, SelectA, Add, R6in, End.

389_Multiple bus architecture.png


Related Discussions:- Multiple bus architecture - computer architecture

Advantages to companies adopting call centres, Advantages to companies adop...

Advantages to companies adopting call centres Computer systems have allowed companies to set up call centres in other nations where potential cost savings can be made. This, of

Define signal and component of obejct oriented modeling, Define about sign...

Define about signal and component of obejct oriented modeling A signal is a specification of an asynchronous stimulus communicated among instances. A component is a physical

Define interrupt processing, Q. Define Interrupt Processing? On complet...

Q. Define Interrupt Processing? On completion of execution of an instruction machine checks whether there is any pending interrupt request for interrupts which are enabled. If

Determine what is the frame rate and frame duration, (i)  A multiplexer com...

(i)  A multiplexer combines four 100-Kbps channels using a time slot of 4 bits. Each Frame has the size of 16 bits. a)  Show the output with the four inputs as shown in the figu

What are the largest UDP messages, What are the largest UDP messages that c...

What are the largest UDP messages that can fit into single Ethernet frame? UDP utilizes IP for delivery. As ICMP UDP packet is encapsulated in IP datagram. Therefore entire UDP

Why a linked list is called a dynamic data structure, Why a linked list is ...

Why a linked list is called a dynamic data structure? What are the advantages of using linked list over arrays?    A linked list is known as a dynamic data structure because it

Mobile cameras, Mobile cameras are characteristically low-resolution Digita...

Mobile cameras are characteristically low-resolution Digital cameras integrated in mobile set. Photographs are characteristically only good enough to show on low resolution mobile

Mini project, give proper code for any kind of project in oop c++

give proper code for any kind of project in oop c++

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd