Multiple bus architecture - computer architecture, Computer Engineering

Assignment Help:

Multiple bus architecture:

One solution to the bandwidth restriction of a single bus is to simply add extra buses. Consider the architecture indicated in given figure that contains N processors, P1 P2 PN, each containing its own private cache, and all linked to a shared memory by B buses BB, B1, B2. The shared memory consists of M interleaved banks M1 M2,MM to permit simultaneous memory requests concurrent access to the shared memory. It ignores the loss in performance that happen if those accesses have to be serialized, which is the case when there is only 1 memory bank. Each processor is linked to every bus and so is each memory bank. When a processor requires accessing a specific bank, it has B buses from which to select. Therefore each processor- memory pair is linked by various redundant paths, which implies that the failure of 1 or more paths can, principally, be tolerated at the cost of some degradation in system performance.

In a multiple bus system many processors may try to access the shared memory simultaneously. To deal with this problem, a policy might be implemented that allocates the available buses to the processors making requests to memory. In particular case, the policy might deal with the case when the number of processors exceeds from the B. For performance point of view this allocation has to be performed by hardware arbiters which, as we will see, add significantly to the difficulty of the multiple bus interconnection networks.

PCout, R=B, MARin, Read, IncPC

  • WFMC
  • MDRoutB, R=B, IRin
  • R4out, R5outB, SelectA, Add, R6in, End.

389_Multiple bus architecture.png


Related Discussions:- Multiple bus architecture - computer architecture

Accept commands from the user, Your shell must accept commands from the use...

Your shell must accept commands from the user. The first step to implement this will be reading a line of input. This section will focus on what to do with the line of input after

Explain dial tone and ringing tone in strowger telephony, Explain Dial Tone...

Explain Dial Tone and Ringing Tone in strowger telephony. Dial Tone: it is used to indicate that the exchange is ready to recognize dialed digits by the subscriber. The subsc

Describe the von neumann architecture, Describe the VON NEUMANN ARCHITECTUR...

Describe the VON NEUMANN ARCHITECTURE Most  of  present  computer  designs  are  based  on  idea  developed  by  John  vonNeumann referred to as the VON NEUMANN ARCHITECTURE. V

How the simulation is done, How the simulation is done Data is entered ...

How the simulation is done Data is entered into the computer and simulation is run. The below scenarios may be tried out: -  Timing of lights varied to see how traffic flow

Sort, quick sort working

quick sort working

Sorting algorithms, Two way merge sort for 84,83,78,90,23,123,98,159,8,200

Two way merge sort for 84,83,78,90,23,123,98,159,8,200

What are the logic micro-operations, Q. What are the Logic Micro-operations...

Q. What are the Logic Micro-operations? Logic operations are fundamentally binary operations that are performed on string of bits stored in the registers. For a logic micro-ope

What are the two aspects of locality of reference, What are the two aspects...

What are the two aspects of locality of reference? Define them. Two aspects of locality of reference are temporal aspects and spatial aspect. Temporal aspect is that a r

Explain about annotational notations, Explain about Annotational Notations ...

Explain about Annotational Notations These notations may be applied to describe remark and illuminate about any element in the model. They are considered as explanatory of U

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd