Multiple bus architecture - computer architecture, Computer Engineering

Assignment Help:

Multiple bus architecture:

One solution to the bandwidth restriction of a single bus is to simply add extra buses. Consider the architecture indicated in given figure that contains N processors, P1 P2 PN, each containing its own private cache, and all linked to a shared memory by B buses BB, B1, B2. The shared memory consists of M interleaved banks M1 M2,MM to permit simultaneous memory requests concurrent access to the shared memory. It ignores the loss in performance that happen if those accesses have to be serialized, which is the case when there is only 1 memory bank. Each processor is linked to every bus and so is each memory bank. When a processor requires accessing a specific bank, it has B buses from which to select. Therefore each processor- memory pair is linked by various redundant paths, which implies that the failure of 1 or more paths can, principally, be tolerated at the cost of some degradation in system performance.

In a multiple bus system many processors may try to access the shared memory simultaneously. To deal with this problem, a policy might be implemented that allocates the available buses to the processors making requests to memory. In particular case, the policy might deal with the case when the number of processors exceeds from the B. For performance point of view this allocation has to be performed by hardware arbiters which, as we will see, add significantly to the difficulty of the multiple bus interconnection networks.

PCout, R=B, MARin, Read, IncPC

  • WFMC
  • MDRoutB, R=B, IRin
  • R4out, R5outB, SelectA, Add, R6in, End.

389_Multiple bus architecture.png


Related Discussions:- Multiple bus architecture - computer architecture

Explain segment registers in bus interface unit, Q. Explain Segment Registe...

Q. Explain Segment Registers in bus interface unit? These are very significant registers of CPU. Why? We will answer this later. In 8086 microprocessor memory is a byte organiz

Process of breadth first search, Process of Breadth first search: It's...

Process of Breadth first search: It's very useful to think of this search as the evolution of the given tree, and how each string of letters of word is found via the search in

Define hypertext verses hypermedia briefly, Define Hypertext verses Hyperme...

Define Hypertext verses Hypermedia briefly. Hypertext is fundamentally the same as regular text- this can be stored, read, searched or edited along with a significant exception

Show the liability of cpu in interrupt cycle, Q. Show the liability of CPU ...

Q. Show the liability of CPU in interrupt cycle? In the interrupt cycle the liability of CPU/Processor is to ensure whether any interrupts have happened checking presence of in

Multithreaded architecture, Multithreaded Architecture:  It is clear now th...

Multithreaded Architecture:  It is clear now that if we give many contexts to multiple threads, then processors with multiple contexts are known as multithreaded systems. These sys

What are the main aspects available in all word processors, What are the Ma...

What are the Main aspects available in all word processors -  Ability to set page size and page orientation -  Ability to change font size and font style (for example Arial,

What is parsing, What is parsing? Parsing is the process of analyzing a...

What is parsing? Parsing is the process of analyzing a text, formed of a sequence of tokens, to find out its grammatical structure regarding a specified formal grammar. Parsing

Message passing programming, Message passing is possible the most widely us...

Message passing is possible the most widely used parallel programming paradigm these days. It is the most portable, natural and efficient scheme for distributed memory systems. It

Microprocessors and interfaces, #question.write cycle timing diagram for ma...

#question.write cycle timing diagram for maximum mode of 8086 microprocessor.

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd