Multiple bus architecture - computer architecture, Computer Engineering

Assignment Help:

Multiple bus architecture:

One solution to the bandwidth restriction of a single bus is to simply add extra buses. Consider the architecture indicated in given figure that contains N processors, P1 P2 PN, each containing its own private cache, and all linked to a shared memory by B buses BB, B1, B2. The shared memory consists of M interleaved banks M1 M2,MM to permit simultaneous memory requests concurrent access to the shared memory. It ignores the loss in performance that happen if those accesses have to be serialized, which is the case when there is only 1 memory bank. Each processor is linked to every bus and so is each memory bank. When a processor requires accessing a specific bank, it has B buses from which to select. Therefore each processor- memory pair is linked by various redundant paths, which implies that the failure of 1 or more paths can, principally, be tolerated at the cost of some degradation in system performance.

In a multiple bus system many processors may try to access the shared memory simultaneously. To deal with this problem, a policy might be implemented that allocates the available buses to the processors making requests to memory. In particular case, the policy might deal with the case when the number of processors exceeds from the B. For performance point of view this allocation has to be performed by hardware arbiters which, as we will see, add significantly to the difficulty of the multiple bus interconnection networks.

PCout, R=B, MARin, Read, IncPC

  • WFMC
  • MDRoutB, R=B, IRin
  • R4out, R5outB, SelectA, Add, R6in, End.

389_Multiple bus architecture.png


Related Discussions:- Multiple bus architecture - computer architecture

#title, what are the applications of microprogramming

what are the applications of microprogramming

Cascade delete options, Create a relationship among Employee and Sales tabl...

Create a relationship among Employee and Sales tables using Emp No. Enforce referential integrity and select both cascade update and cascade delete options. Save the relationship.

Differentiate between motion and shape tween, Question: 1. In Flash, w...

Question: 1. In Flash, what is the purpose of a motion guide layer? 2. Differentiate between Motion and Shape tween. 3. Give the steps to create a layer mask in flash.

Define dma, Define DMA. The transfer of data among a fast storage devic...

Define DMA. The transfer of data among a fast storage device such as magnetic disk and memory if often limited by the speed of the CPU. Removing the CPU from the path and letti

Explain characteristics of the artificial neural networks, Question 1: ...

Question 1: Explain in detail the characteristics of the following artificial neural networks. (a) Recurrent Neural Networks. (b) Self-organising Mapping Neural Networks.

How to set a read or write watch point for a variable, By using Rwatch, Awa...

By using Rwatch, Awatch command in GDB we can set read or write watchpoint for a variable.

What is unique port number, Q. What is Unique port number? A port is an...

Q. What is Unique port number? A port is an extra 16-bit number which uniquely identifies particular service on any given machine on Internet. Port numbers are 16 bit wide, con

Elaborate the various steps in performing a mail merge, COMPUTER FUNDAMENTA...

COMPUTER FUNDAMENTALS 1. Elaborate the various steps in performing a Mail Merge. Perform one mail merge operation for sending invitation for a conference which is being conduc

Communication between memory and the processor, How are instructions sent b...

How are instructions sent between memory and the processor? Both the instruction pointer (IP) and program counter (PC) utilized to holds the memory address of the next inst

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd