Multiple assign statements targeting the same wire, Computer Engineering

Assignment Help:

What logic is inferred when there are multiple assign statements targeting the same wire?

It's illegal to specify multiple assign statements to the same wire in a synthesizable code that will become  an  output  port  of  module.  Synthesis  tools  give  a  syntax  error  that  a  net  is  being driven by more than one source.

Illegal Code

Wire temp;

Assign temp = in1 & in2;

Assign temp = in3 & in4;

However, it is legal to drive a three-state wire by multiple assign statements.

Legal code

Wire temp;

Assign temp = enable1? (In1 & in2): 1'bz;

Assign temp = enable2? (In3 & in4): 1'bz

 


Related Discussions:- Multiple assign statements targeting the same wire

Explain compiler, What is compiler? A system software program known as ...

What is compiler? A system software program known as a compiler translates the high-level language program into a suitable machine language program having instruction such as t

Components of a 3-tier client server, What are the essential components of ...

What are the essential components of a 3-tier client server In a three-tier or multi-tier environment, the client executes the presentation logic (the client). The business log

Computer architecture, what is complex instruction set computer and reduce...

what is complex instruction set computer and reduced complex instruction set computer

Define congestion, Define Congestion. Congestion: This is uneconomic ...

Define Congestion. Congestion: This is uneconomic to give sufficient equipment to carry all the traffic which could possibly be offered to a telecommunication system. Inside

Staircase, What is the aim of a stair case light is controlled by two switc...

What is the aim of a stair case light is controlled by two switches one at the top of the stairs and another at the bottom of the stair

Design a 3-bit counter using sequential logic, Q. Design a 3-bit counter us...

Q. Design a 3-bit counter using sequential logic with following counting sequence using JK- flip-flops which counts the sequence 0, 3, 2, 7, 5 and repeat.

General registers in a processor, In this segment, we will give very brief ...

In this segment, we will give very brief details of registers of a RISC system known as MIPS. MIPS is a register-to-register or load/store architecture and employs three address

Define seek time and latency time, Define seek time and latency time. ...

Define seek time and latency time.  The time taken by the head to move to the appropriate cylinder or track is known as seek time. Once the head is at right track, it must wai

What is event-based simulator, Event-based Simulator Digital  Logic  S...

Event-based Simulator Digital  Logic  Simulation  method  sacrifices  performance  for  rich  functionality:  each active signal  is  calculated  for  every  device  it  propa

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd