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What logic is inferred when there are multiple assign statements targeting the same wire?
It's illegal to specify multiple assign statements to the same wire in a synthesizable code that will become an output port of module. Synthesis tools give a syntax error that a net is being driven by more than one source.
Illegal Code
Wire temp;
Assign temp = in1 & in2;
Assign temp = in3 & in4;
However, it is legal to drive a three-state wire by multiple assign statements.
Legal code
Assign temp = enable1? (In1 & in2): 1'bz;
Assign temp = enable2? (In3 & in4): 1'bz
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flow chart
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