Modes of 8254-microprocessor, Assembly Language

Assignment Help:

Modes of 8254 :

 

1632_modes of 8254.jpg

Mode 0 (Interrupt on Terminal Count)-GATE which value is 1 enables counting and GATE  which value is 0 disables counting, and GATE put not effect on OUT. The contents of the CR are transferred to CE on the first CLK pulse after CR is written into by the processor, unrelated of the signal on the GATE pin. Pulse that loads CE is not included in the count. OUT would low when there is an output to the control register and remains low till the count goes to 0.Primarily, Mode 0 is for event counting.

Mode 1 (Hardware Re -triggerabic  One-Shot)-After  CR has been loaded  with N, a 0-to-1  transition  on GATE will cause CE to be loaded, a one-to-zero transition  at OUT, and the count to start. When the count reaches to zero OUT will go high so producing a negative-going OUT pulse N clock periods long.

Mode 2 (Periodic Interval Timer)-after loading CR with N, a transfer is occur from CR to CE on the next clock pulse. OUT goes from one  to zero when the count becomes one and remains low for o1 CLK pulse; then it returns to 1 and CE is reloaded from CR, so  giving a negative pulse at OUT after each N clock cycles. GATE that value 1 enables the count and GAT that value is 0 disables the count. A 0-to-1 transition on GATE also causes the count to be reinitialized on the next clock pulse. This mode is utilized to provide a programmable periodic interval timer.

Mode 3 (Square-Wave Generator)-It is likewise to mode 2 except that OUT goes low when half the first count is reached and remains low till the count becomes zero. So the duty cycle is changed. As like before, GATE enables and disables the count and a zero to one transition on GATE reinitializes the count. This mode can be utilized for baud rate generation.

Mode 4 (Software-Triggered  Strobe)-It is likewise to mode 0 except that OUT is high while the counting is taking place and generate a one-clock-period negative pulse when the count reaches zero.

Mode 5 (Hardware-Triggered Strobe-Retriggerabic)-After CR is loaded, a O-to-I transition on GATE will cause a transfer from CR to CE during the next CLK pulse. OUT will be high in the time counting but will go low for one CLK period when the count becomes zero. GATE may reinitialize counting at any time.

For all modes, if the starting count is zero, it will be interpreted as216 or104 depending on the format of the count. The above descriptions were just to provide a whole idea of the operation of the 8254 in the several modes.

 

 


Related Discussions:- Modes of 8254-microprocessor

Using straight line method for depreciation, Request a depreciation of the...

Request a depreciation of the item, year of purchase, cost of item, number of years to be depreciated (estimated life ) and,the method of depreciation . Method of depreciation sh

Project ideas, can u please give me ideas on Assembly Language Projects usi...

can u please give me ideas on Assembly Language Projects using Nasm

Dma hardware (8237 dmac)-microprocessor, DMA Hardware (8237 DMAC) : ...

DMA Hardware (8237 DMAC) :   1)Processor contain HOLD/HOLD Acknowledge lines to interact with 8237 o   DMAC can achieve control of ISA bus by asserting HOLD o   P

More Sentence Sense, When Seen in the choir, Terry was the picture of an an...

When Seen in the choir, Terry was the picture of an angelic devil. I have to underline the predicate twice

Read architecture:look aside cache-microprocessor, Read Architecture : Look...

Read Architecture : Look Aside Cache In "look aside" cache architecture the main memory is located conflictingthe system interface. Both the cache main memory sees a bus cycle

Program on fibonacci series , Write a program to calculate the first 20 num...

Write a program to calculate the first 20 numbers of Fibonacci series. Use the stack (memory) to store the calculated series. Your debugger output should look like the following sc

8088 timing system diagram-Microprocessor, 8088  Timing System Diagram ...

8088  Timing System Diagram The 8088 address/data  bus is divided  in 3 parts (a) the lower 8 address/data  bits, (b) the middle 8 address bits, and (c) the upper 4 status/

Minecraft/Terminal issues, I am running a small minecraft server off of my ...

I am running a small minecraft server off of my old mac mini, and am having a big issue. My computer isn''t very good, and even just running this server is an issue. I use a comma

Aad-arithmetic instruction-microprocessor, AAD: ASCII Adjust for Division ...

AAD: ASCII Adjust for Division though the names of these 2 instructions (AAM and AAD) seem to be same, there is many difference between their functions. The AAD instruction conver

ISBN CHECK, How do i convert a asci number to numerals?

How do i convert a asci number to numerals?

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd