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1. Consider these two potential additions to the MIPS instruction set and explain how they would restrict pipelining.
a) cp d1(r1), d2(r2)
copy contents of word at address c address contents of r2 plus offset d2 into address contents of r1 plus displacement d2.
b) incr d2(r2)
adds one to the contents of word at address contents of r2 plus offset d2.
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can we solve the problem using bounded buffer space if the propagation delay is arbitrarily large ?
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