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MIPS - computer architecture:
The MIPS ISA, so far
3 instruction formats
Fixed 32-bit instruction
3-operand, load-store architecture
32 general-purpose register (floating point, integer)
R0 always equal 0
Register are 32 -bits wide (word)
2-speacial purpose register LO & HI, because division and multiply generate more then 32-bits
Register instant and base+ displacement addressing mode.
draw 4 bit binary to gray code
Process: pid start time end time priority timeslice list of CPU bursts list of IO bursts (the number of IO burst will always be 1 less than the number of CPU
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