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MIPS - computer architecture:
The MIPS ISA, so far
3 instruction formats
Fixed 32-bit instruction
3-operand, load-store architecture
32 general-purpose register (floating point, integer)
R0 always equal 0
Register are 32 -bits wide (word)
2-speacial purpose register LO & HI, because division and multiply generate more then 32-bits
Register instant and base+ displacement addressing mode.
Determine the synchronization of bits The synchronization provided by use of start and stop bits, an extra bit known as a parity bit may optionally be transmitted along with th
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Subtract -27 from 68 using 2's complements. Ans. By using 2's complement 68-(-27)= 68-(-27) 2's complement representation of 68 = 01000100(64+4) 2's complement representatio
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draw 4 bit binary to gray code
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