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Q. When the J and K inputs of a JKFF are tied to logic 1, this device is known as a divide-by-2 counter. Complete the timing diagram shown in Figure for this counter.
Design a DC motor control system to run the 48V DC motor at 40rpm up to max load of the motor. You are responsible for designing the control of a 24V supply along with the speed s
Q. Determine voltage and current gains for the CE BJT amplifier shown in Figure with the following parameters: R 1 = 30,000, R 2 = 9000 ,R C = 750 ,R E = 250 , R L = 1000
Explain the delay model based on logical effort often used in estimating delays in logic cells. Hence use the model to predict the delay of a 4-input NOR logic cell with a 3 times
Operation - unijunction transistor: Operation : Imagine that the emitter supply voltage is turned biased and a small emitter reverse current flows. Then the intrinsic stand
Q. Explain working of Biased Clamper? Biased Clamper : The circuit of a positively biased clamper is shown in the figure. During the negative half cycle of the input signal the
Vital parameters of regulator quality: 1. The output voltage's temperature coefficient of is the change in output voltage with temperature (perhaps averaged over a certain tem
Magnetic permeability and the B/H curve To measure the relationship between field strength H and flux density B for a material, a sample is made into a closed ring and a magne
Q. Two three-phase generators are supplying to a common balanced three-phase load of 30 kW at 0.8 power factor lagging. The per-phase impedance of the lines connecting the generato
Determine the load - Thevenins Equivalent Circuit: Determine the load for which the source shall transfer the maximum power if load is connected across the terminal A and B, u
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