Interrupt - driven input-output, Computer Engineering

Assignment Help:

Q. Interrupt - Driven Input-output?

Problem with programmed I/O is that processor has to wait a long time for I/O interface to see whether a device is free or waits until completion of I/O. Result is that the performance of processor goes down extremely. What is the solution? What about processor going back to do other useful work without waiting for I/O device to finish or get freed up? However how will processor be intimated about completion of I/O or a device is ready for I/O? A well-organized mechanism was considered for this which is referred to as interrupt-driven I/O. In this mechanism provision of interruption of processor work once device has completed I/O or when it's ready for I/O has been provided.

Interrupt-driven I/O mechanism for transferring a block of data is displayed in Figure 5(b). Please note after issuing a read command (for input) CPU goes off to do some other useful work whereas I/O interface proceeds to read data from connected device. On completion of an instruction cycle CPU checks for interrupts (that will happen when data is in data register of I/O interface and it now requires CPU's attention). Now CPU saves important register and processor status of executing program in a stack and requests I/O device to provide its data that is placed on data bus by I/O device. After taking needed action with data CPU can go back to program it was executing before interrupt.


Related Discussions:- Interrupt - driven input-output

Sequential execution of instructions in risc, Q. Sequential Execution of In...

Q. Sequential Execution of Instructions in RISC? Let's describe pipelining in RISC with an illustration program execution sample. Take the given program (R denotes register).

What is an identification method, An identification method notifies Robot h...

An identification method notifies Robot how to recognize the values to compare during record and playback.

What is tcas, tCAS is the number of clock cycles required to access a parti...

tCAS is the number of clock cycles required to access a particular column of data in SDRAM. CAS latency is the column address strobe time, sometimes referred to as tCL.

What are the two primary models of supply chain management, What are the tw...

What are the two primary models of Supply Chain Management? The Two Primary models of Supply Chain Management are:- 1.  Porter's Value Chain Model 2. Supply Chain Model

Evaluate physical address of top of stack, Q. Evaluate Physical address of ...

Q. Evaluate Physical address of top of stack? Value of stack segment register (SS) = 6000h Value of stack pointer (SP) which is Offset = 0010h  So Physical address of top

Explain the trackball and thumbwheel devices, Explain the Trackball and Thu...

Explain the Trackball and Thumbwheel devices  Joysticks A joystick consists of a small, vertical lever (called the stick) mounted on a base that is used to steer the screen

OR, importance of duality concep? Article Source: http://EzineArticles.co...

importance of duality concep? Article Source: http://EzineArticles.com/4133733

Determine about the term- voice synthesis, Voice synthesis Loud speakers ...

Voice synthesis Loud speakers and special software are used to output information in the form of sound to help blind and partially-sighted people; it also helps people who have d

What is spread spectrum, Question: (a) In order to encourage the develo...

Question: (a) In order to encourage the development mobile technologies, Europe has opted for standardisation. What is the rationale behind this? Provide concrete examples of h

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd