Intel architecture – 64, Computer Engineering

Assignment Help:

IA-64 (Intel Architecture-64) is a 64-bit processor architecture created in cooperation by Hewlett-Packard and Intel applied by processors like Itanium. The objective of Itanium was to create a 'post-RISC era' architecture employing EPIC (Explicitly Parallel Instruction Computing).

1 EPIC Architecture

In this system a complex decoder system inspects every instruction as it flows by pipeline and sees that which is able to be fed off to function in parallel across available execution units for example a series of instructions for executing computations.

 A = B + C and

 D = F + G

These would be independent of one another and won't affect one another and so they can be fed in 2 numerous execution units and run in parallel. The capability to extract instruction level parallelism (ILP) from instruction stream is necessary for high-quality performance in a modern CPU.

Forecasting which code can and which cannot be divide up this way is a exceptionally complicated task. In many cases inputs to one line are dependent on output from another however only if some other condition is true. For illustration Think about slight modification of illustration noted before A = B + C IF A==5 THEN D = F + G. In this case calculations stay independent of other however second command needs results from first calculation in order to know if it must be run at all.

In these cases circuitry on CPU generally 'guesses' what condition will be. In something such as 90% of all cases an IF would be taken suggesting that in our illustration second half of command can be safely fed in another core. But getting guess wrong can cause a important performance hit when result has to be thrown out in addition CPU waits for results of 'right' command to be computed. Much of improving performance of modern CPUs is because of better prediction logic however recently improvements have begun to slow. Branch prediction accurateness has reached figures in excess of 98% in recent Intel architectures and raising this figure can only be attained by devoting more CPU die space to branch predictor a self-defeating tactic since it will make CPU more costly to manufacture.

IA-64 instead depends on compiler for this task. Even before program is fed in CPU compiler inspects code and makes same sorts of decisions which would otherwise happen at 'run time' on chip itself. Once it has determined what paths to take it collects up instructions it knows can be run in parallel and bundles them in one larger instruction and then stores it in that form in program.


Related Discussions:- Intel architecture – 64

Determine the performance of a parallel algorithm, Q. Determine the perform...

Q. Determine the performance of a parallel algorithm? One more method of determining the performance of a parallel algorithm can be performed after calculating a parameter know

Difference between shadow and override in programming, Overriding tell us o...

Overriding tell us only the methods, but shadowing tells us the entire element.

Applied physics, #what is nicol prism.its construction and working

#what is nicol prism.its construction and working

Steps uesd in quine mckluskey method, Q. Steps uesd in quine mckluskey meth...

Q. Steps uesd in quine mckluskey method? Step I: Build a table in that every term of expression is represented in row (Expression must be in SOP form). Terms can be expres

Layers of distributed system architecture, Q. Layers of Distributed System ...

Q. Layers of Distributed System architecture? Layers of Distributed System architecture are: Presentation Layer is actual user interface. This layer receives input and

Variable or compound expression - unification algorithm, Variable or compou...

Variable or compound expression - Unification algorithm: Here some things to note regarding this method are:  (i) There if really trying to match a constant to a different

Functions to remove common walls, We must also be able to remove common wal...

We must also be able to remove common walls between two cells. Write the function removewalls that accepts two cells and removes the wall that is common between the two (hint: any

Determine the complete or gate and and gate decoder, Q. Determine the comp...

Q. Determine the complete OR gate and AND gate decoder count for an IC memory with 4096 words of 1 bit each, using the Linear select memory organization and Two dimensional Memory

Obstacles to is implementation - information system, Obstacles to IS implem...

Obstacles to IS implementation While information systems are now becoming the norm in most organisations the journey to this point has been a difficult one. Even in the 21st c

Show the bus and memory transfers, Q. Show the Bus and Memory Transfers? ...

Q. Show the Bus and Memory Transfers? A digital computer has many registers and rather than connecting wires amid all registers to transfer information between them a common bu

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd