Instruction issue degree in superscalar processing, Computer Engineering

Assignment Help:

Q. Instruction Issue degree in superscalar processing?

The major concept in superscalar processing is how many instructions we are able to issue per cycle. If we are able to issue k number of instructions for each cycle in a superscalar processor then that processor is known as a k-degree superscalar processor. If we wish to exploit the full parallelism from a superscalar processor then k instructions should be executable in parallel.

For illustration, we think about a 2-degree superscalar processor with 4 pipeline phases for instruction cycle which means instruction fetch (IF), decode instruction (DI), fetch the operands (FO), execute the instruction (EI) as displayed in Figure below. In this superscalar processor 2 instructions are issued per cycle as displayed in Figure below. Here, 6 instructions in 4 stage pipelines have been executed in 6 clock cycles. Under ideal situations, after steady state, two instructions are being executed for each cycle.

917_Instruction Issue degree in superscalar processing.png

Figure: Superscalar processing of instruction cycle in 4-stage instruction pipeline


Related Discussions:- Instruction issue degree in superscalar processing

How many flip-flops are required to construct mod 30 counter, How many flip...

How many flip-flops are required to construct mod 30 counter ? Ans. Mod - 30 counter +/- requires 5 Flip-Flop as 30 5 . Mod - N counter counts overall ' N ' number of state

Features and utilities available in java, Explain the features and utilitie...

Explain the features and utilities available in java, which makes it suitable for developing e-commerce applications.     1.  In a network, the transmission of passive informati

Network throughput-network properties, Network throughput It is an indi...

Network throughput It is an indicative measure of the point carrying capacity of a network. It is distinct as the total number of messages the network can transmit per unit tim

Explain difference between risc and cisc, RISC-Means Reduced Instruction Se...

RISC-Means Reduced Instruction Set Computer. A RISC system has decreased number of instructions and more significantly it is load store architecture were pipelining can be executed

What is interpreter, Q. What is interpreter? An interpreter translates ...

Q. What is interpreter? An interpreter translates each high-level-language statement into its equivalent set of machine-language instructions, which are then executed right awa

Show matrix multiplication problem, Q. Show Matrix Multiplication Problem? ...

Q. Show Matrix Multiplication Problem? Let there be 2 matrices M1 and M2 of sizes a x b and b x c correspondingly. If we multiply M1 and M2 product matrix O will be of size a x

Interconnection networks, As in PRAM there was not any direct communication...

As in PRAM there was not any direct communication medium between processors so a different model called as interconnection networks have been considered. In the interconnection net

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd