Input-output techniques, Computer Engineering

Assignment Help:

After going through details of device interfaces next point to be discussed is how the interface can be used to support I/O from devices. Binary information received from an external device is generally stored in memory for later processing. Information transferred from central computer in an external device initiates in memory unit. Data transfer between central computer and I/O devices can be handled in some modes. 3 techniques are possible for I/O operation. These are:

  • Programmed input/output
  • Interrupt driven input/output
  • Direct memory access

Figure below gives an general idea of these 3 techniques:

1004_INPUT-OUTPUT TECHNIQUES.png

Figure: Overview of the three Input/ Output

In programmed I/O, I/O operations are fully controlled by processor. The processor executes a program which initiates, directs and terminate an I/O operation. It needs a little special I/O hardware however is quite time consuming for processor as processor has to wait for slower I/O operations to finish. 

With interrupt driven I/O when interface decides that device is ready for data transfer it produces an interrupt request to the computer. Upon detecting external interrupt signal processor stops the task it was processing and branches to a service program to process I/O transfer and then returns to task it was initially performing that result in waiting time by the processor being reduced.

With both interrupt-driven and programmed I/O processor is responsible for extracting data from main memory for output and storing data in main memory during input. What about having a substitute where I/O device may directly store data or retrieve data from memory? This alternative is called direct memory access (DMA). In this mode I/O interface and main memory exchange data directly without involvement of processor.

2405_INPUT-OUTPUT TECHNIQUES1.png

Figure: Three techniques of I/O


Related Discussions:- Input-output techniques

Critical path analysis, Given the information provided in Table 1: ...

Given the information provided in Table 1: Prepare an Activity on the Node (AON) Network Diagram ( I recommend you  use MS Project or any drawing tool); Prepare

Explain the term - instruction execution, Explain the term - Instruction ex...

Explain the term - Instruction execution We  know  that  the  fundamental  function  performed  by  a  computer  is  the  execution  of  program. The program that is to be exec

Two parallel fetch-implement, Take a CPU that shows two parallel fetch-impl...

Take a CPU that shows two parallel fetch-implement pipelines for superscalar processing. Determine the performance improvement over scalar pipeline processing and no-pipeline proce

Define smtp, SMTP Simple Mail Transfer Protocol, a protocol for sending...

SMTP Simple Mail Transfer Protocol, a protocol for sending e-mail messages among servers. Most e-mail systems that send mail over the Internet use SMTP to send messages from si

What is public-key infrastructures, a. What are the differences among conve...

a. What are the differences among conventional signatures and digital signatures? Write a short note on "Attacks on digital signature". b. What is Public-Key Infrastructures

Uniform memory access model (uma), Uniform Memory Access Model (UMA) In...

Uniform Memory Access Model (UMA) In this model, the main memory is uniformly shared by all processors in multiprocessor systems and each processor has equal access time to sha

Procedure level- levels of parallel processing, Procedure Level Here, p...

Procedure Level Here, parallelism is accessible in the form of parallel executable procedures. In this situation, the design of the algorithm plays a main role. For example eac

Is it possible to decrease clock skew to zero, Is it possible to decrease c...

Is it possible to decrease clock skew to zero? Describe your answer? Even if there are clock layout strategies (H-tree) which can into theory reduce clock skew to zero by havi

Design requirements of combinational logic, What are the requirements to de...

What are the requirements to design Combinational Logic ? Ans . Design Requirements of Combinational Logic:- (i) By the specifications of circuit, we find out the

Flat, nfa significance

nfa significance

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd