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You are required to program (in a high level language such as C, C++, Java) and implement a cache simulator which will have the following inputs and outputs:-
INPUTS OUTPUTS
Memory trace <=> smalltex.din (during code development microtex.din - see later) and each address is the current address, in RAM, of a Byte required by the CPU.
Cache size <=> size of cache in bytes
Block size <=> size of blocks in bytes
Degree of associativity <=> direct (1-way), 2-way, 4-way, 8-way, and fully associative
Replacement policy <=> Random and LRU are to be implemented.
Total miss rate = compulsory + capacity + conflict miss rates.
* The memory trace file (smalltex.din) is located at /home/csiii/csiiilib/arc/smalltex.din or /home/3rd/csiiilib/arc/smalltex.dinCopy this file to your arc directory where you will be running your assignment from.
List the requirements needed to design a trigger. The requirements are:- Specifying when a trigger is to be implemented. State the actions to be taken when the trigger im
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