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Q. Illustrate the Cache Memory Operation?
It comprises a copy of a part of main memory contents. When a program is running and CPU tries to read a word of memory (instruction or data) a check is made to decide if word is in cache. If so that word is delivered to CPU from cache. If not then a block of main memory comprising some fixed number of words including requested word is read in the cache and then requested word is delivered to CPU. Due to the feature of locality of reference when a block of memory word is fetched in cache to satisfy a single memory reference it is expected that there will soon be references to other words in that block. Which is the next time CPU attempts to read a word it's very probable that it finds it in cache and saves time required to read word from main memory.
Various computer systems are designed to have two separate cache memories known as data cache and instruction cache. Instruction cache is used for storing program instruction and data cache is used for storing data. This allows faster identification of availability of accessed word in cache memory as well as it helps in further improving processor speed. Several computer systems are also designed to have multiple levels of caches (like level one and level two caches generally referred to as L1 and L2 caches). L1 cache is smaller than L2 cache and is used to store more often accessed data/instruction as compared to those in L2 cache.
For the circuit demonstrated below, what is the Maximum Frequency of Operation? Are there any hold time violations for FF2? When yes, how do you modify the circuit to ignore them?
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Q. Write a program to perform multiplication of two numbers in specified radix. Check that entered numbers are in specified radix or not else error message should be displayed.
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