Q. Illustrate Organisation of DRAM Chip?

The given figure is a typical organisation of 16 mega bit DRAM. It displays a typical organisation of 2048 × 2048 × 4 bit DRAM chip. Memory array in this organisation is a square array which is (2048 × 2048) words of 4 bits each.

Every element that consists of 4 bits of array is connected by horizontal row lines and vertical column lines. Horizontal lines are connected to select input in a row while vertical line is connected to output signal through a sense amplifier or data in signal by data bit line driver. Please note that selection of input from this chip needs:

• Row address selection specifying present address values A₀ to A₁₀ (11 address lines only). For the rows it is stored in row address buffer by decoder.
• Row decoder selects required row.
• Column address buffer is loaded with column address values that are also applied to through A0 to A10 lines only. Please note these lines must contain values for column.
• This job will be done by a change in external signal R¯A¯S¯ (Row address Strobe) since this signal is high at rising edge of clock.
• C¯A¯S¯ (Column address Strobe) causes column address to be loaded with these values.
• Every column is of 4 bits which is those need 4 bit data lines from input/output buffer. On memory write operation data in bit lines being activated while on read sense lines being triggered.
• This chip needs 11 address lines (in place of 22), 4 data in and out lines and other control lines.
• As there are 11 row address lines as well as 11 column address lines and every column is of 4 bits so size of chip is 2¹¹ × 2¹¹ ×4 = 2048 × 2048 ×4 = 16 mega bits. On increasing address lines from 11 to 12 we have 2¹² × 2¹² ×4 = 64 mega bits which are an increase of a factor of 4. So possible sizes of such chips can be 16K, 256K, 1M, 4M, 16M and so on.
• Refreshing of chip is done periodically using a refresh counter. One simple scheme of refreshing may be to disable read-write for some time and refresh all rows one by one.