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Q. Illustarte Basic Flip-flops?
Let's first see a ordinary latch. A latch or flip-flop can be created employing two NOR or NAND gates. Figure (a) presents logic diagram for S-R latch using NOR gates. Latch has two inputs S and R for set and reset respectively. When output is Q=1 and Q¯ =0, latch is said to be in set state. Whereas if Q=0 and Q¯ =1 it's in reset state. Usually outputs Q and Q¯ are complement of one another. When both inputs are equivalent to 1 at same time an undefined state results as both outputs are equivalent to 0.
For JK flip flop with J=1, K=0, the output after clock pulse will be ? Ans. The output will be 1 after clock pulse.
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Reduce the following equation using k-map Y = BC‾D‾ + A‾BC‾D + ABC‾D + A‾BCD + ABCD Ans. Multiplying the first term with (A+A') Y = A'BC'D' + ABC'D' + A'BC'D + ABC'D + A'BCD + A
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describe the block diagram of a system showing the following microprocessor memory system buses
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