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Q. Illustarte Basic Flip-flops?
Let's first see a ordinary latch. A latch or flip-flop can be created employing two NOR or NAND gates. Figure (a) presents logic diagram for S-R latch using NOR gates. Latch has two inputs S and R for set and reset respectively. When output is Q=1 and Q¯ =0, latch is said to be in set state. Whereas if Q=0 and Q¯ =1 it's in reset state. Usually outputs Q and Q¯ are complement of one another. When both inputs are equivalent to 1 at same time an undefined state results as both outputs are equivalent to 0.
DeMorgan's first theorem shows the equivalence of which logic gate ? Ans. DeMorgan's first theorem depicts the equivalence of NOR gate and Bubbled AND gate. For De Morgan's
Ask question #Minimum Write a program to mask bits D3D2D1D0 and to set bits D5D4 and to invert bits D7D6 of the AX register. 100 words accepted#
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