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Q. Illustarte Basic Flip-flops?
Let's first see a ordinary latch. A latch or flip-flop can be created employing two NOR or NAND gates. Figure (a) presents logic diagram for S-R latch using NOR gates. Latch has two inputs S and R for set and reset respectively. When output is Q=1 and Q¯ =0, latch is said to be in set state. Whereas if Q=0 and Q¯ =1 it's in reset state. Usually outputs Q and Q¯ are complement of one another. When both inputs are equivalent to 1 at same time an undefined state results as both outputs are equivalent to 0.
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Define parity generator During transmission, at sending end the message is applied to a parity generator, where the needed bit is formed.
Define Polling. A Polling process is used to recognize the highest priority source by software means. In this process there is one common branch address for all interrupts.
. weather (windy, rainy or sunny) 2. how much money you have (rich or poor) 3. whether your parents are visiting (yes or no)
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Q. Show the Features added in message passing interface-2 Input/output Single-sided operations for remote memory access Binding for C++ Dynamic process managem
write algorithm and draw flowchart for exchange the values of two variables.
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