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Q. Illustarte Basic Flip-flops?
Let's first see a ordinary latch. A latch or flip-flop can be created employing two NOR or NAND gates. Figure (a) presents logic diagram for S-R latch using NOR gates. Latch has two inputs S and R for set and reset respectively. When output is Q=1 and Q¯ =0, latch is said to be in set state. Whereas if Q=0 and Q¯ =1 it's in reset state. Usually outputs Q and Q¯ are complement of one another. When both inputs are equivalent to 1 at same time an undefined state results as both outputs are equivalent to 0.
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Use linear activation function and Hebbian learning for a SLFF network to attempt to learn the following two sets of patterns. Why can the patterns be learned, or why can they not
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How many select lines will a 16 to 1 multiplexer will have ? Ans. For 16 to 1 MUX four select lines will be needed to select 16 (2 4 ) inputs.
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