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Q. Illustarte Basic Flip-flops?
Let's first see a ordinary latch. A latch or flip-flop can be created employing two NOR or NAND gates. Figure (a) presents logic diagram for S-R latch using NOR gates. Latch has two inputs S and R for set and reset respectively. When output is Q=1 and Q¯ =0, latch is said to be in set state. Whereas if Q=0 and Q¯ =1 it's in reset state. Usually outputs Q and Q¯ are complement of one another. When both inputs are equivalent to 1 at same time an undefined state results as both outputs are equivalent to 0.
The do while Loop This is very similar to the while loop except that the test occurs at the end of the loop body. This guarantees that the loop is executed at least once before
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Q. What do you mean by Daisy chain? This scheme provides a hardware poll. With this scheme, an interrupt acknowledge line is chain by different interrupt devices. All I/O inter
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Arbitrary categorisation - learning decision trees: Through visualising a set of boxes with some balls in. There if all the balls were in a single box so this would be nicely
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