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Q. Illustarte Basic Flip-flops?
Let's first see a ordinary latch. A latch or flip-flop can be created employing two NOR or NAND gates. Figure (a) presents logic diagram for S-R latch using NOR gates. Latch has two inputs S and R for set and reset respectively. When output is Q=1 and Q¯ =0, latch is said to be in set state. Whereas if Q=0 and Q¯ =1 it's in reset state. Usually outputs Q and Q¯ are complement of one another. When both inputs are equivalent to 1 at same time an undefined state results as both outputs are equivalent to 0.
Explain the Features of Major scheduling algorithms. The Features of Major scheduling algorithms is given below: FCFS - i.e. First come first served scheduli
A component has the time to failure distribution that is modelled as the Weibull distribution with shape parameter 3 and scale parameter of 36 months. This component is planned to
Q. Explain functions of direct memory access? Though CPU intervention in DMA is minimised however it should use path between interfaces that is system bus. So DMA involves an e
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Q. Explain about Parity bit? Parity bit is an error detection bit added to binary data such that it creates total number of 1's in the data either odd or even. For illustration
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Universal Elimination: Here for any sentence, there is A, containing a universally quantified variable, v, just for any ground term, g, so we can substitute g for v in A. Thus
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