How to fix an ASIC-based design from easiest to most extreme?

There are different ways to fix an ASIC-based design as given below:
Initially, assume some reviews fundamentally. A standard-cell ASIC includes at least 2 dozen manufactured layers/masks. A lower layer includes materials making up the real CMOS gates and transistors of the design. The upper from 3 to 6 layers are metal layers used this to connect everything mutually. ASICs, obviously, are not intended to be flexible as an FPGA; nevertheless, significant "fixes" can be made throughout the manufacturing procedure. The progression of possible fixes into the manufacturing life cycle is listed above as follows:

>From easiest to most extreme as: RTL Fix -> Gate Fix -> Metal Fix -> FIB Fix

Obviously, these sorts of fixes are risky and tricky. They are obtainable to the ASIC developer, but should be negotiated and coordinated along with the foundry. ASIC designers who have been by enough of these fixes appreciate the value of adding test and fault-tolerant design characteristics within the RTL code therefore Software Fixes can correct minor silicon problems!