How are problems of clock skew minimized?

Clock skew, when done right, can also benefit a circuit. This can be intentionally introduced to reduce the clock period, at that the circuit will operate accurately, and/or to enhance the setup or hold safety margins. The optimal set of clock delays is founded by a linear program, wherein a setup and a hold constraint appear for every logic path. In that linear program, zero clocks skew is simply a feasible point. Clock skew can be minimized with appropriate routing of clock signal (clock distribution tree) or putting variable delay buffer therefore all clock inputs arrive at similar time.